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Grzegorz Daniluk authored
Reason: h_y was close to the DAC range, on some boards we were unable to lock HPLL. In addition to HPLL modifications, also the phase shifting had to be changed. When offset clock has lower frequency than the ref clock, shifting ref clock produces sampled clock which is shifted in another direction.
0376b6f1
| Name |
Last commit
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Last update |
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| arch/lm32 | ||
| boards/arria | ||
| configs | ||
| dev | ||
| doc | ||
| include | ||
| ipc | ||
| lib | ||
| monitor | ||
| pp_printf | ||
| ppsi @ da4979d6 | ||
| scripts | ||
| sdb-lib | ||
| shell | ||
| softpll | ||
| tools | ||
| .gitignore | ||
| .gitmodules | ||
| COPYING | ||
| Kconfig | ||
| MAKEALL | ||
| Makefile | ||
| Makefile.kconfig | ||
| bigobj.lds | ||
| check-error.c | ||
| revision.c | ||
| system_checks.c | ||
| wrc_main.c | ||
| wrc_ptp.h | ||
| wrs_main.c |