spll: lock offset frequency below the ref frequency

Reason: h_y was close to the DAC range, on some boards we were unable to lock HPLL. In addition to HPLL modifications, also the phase shifting had to be changed. When offset clock has lower frequency than the ref clock, shifting ref clock produces sampled clock which is shifted in another direction.

spll: lock offset frequency below the ref frequency
Reason: h_y was close to the DAC range, on some boards we were unable to lock HPLL. In addition to HPLL modifications, also the phase shifting had to be changed. When offset clock has lower frequency than the ref clock, shifting ref clock produces sampled clock which is shifted in another direction.
0376b6f1 · Grzegorz Daniluk · 1066ae7b · 0376b6f1 · 0376b6f1 · 0376b6f1
Commit 0376b6f1 authored Jul 30, 2015 by Grzegorz Daniluk
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Showing with 8 additions and 8 deletions

spll_helper.c softpll/spll_helper.c +3 -3

spll_main.c softpll/spll_main.c +4 -4

spll_ptracker.c softpll/spll_ptracker.c +1 -1

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--- a/softpll/spll_helper.c
+++ b/softpll/spll_helper.c
@@ -25,8 +25,8 @@ void helper_init(struct spll_helper_state *s, int ref_channel)
 	/* Phase branch PI controller */
 	s->pi.y_min = 5;
 	s->pi.y_max = (1 << DAC_BITS) - 5;
-	s->pi.kp = 150;//(int)(0.3 * 32.0 * 16.0);	// / 2;
-	s->pi.ki = 2;//(int)(0.03 * 32.0 * 3.0);	// / 2;
+	s->pi.kp = -150;//(int)(0.3 * 32.0 * 16.0);	// / 2;
+	s->pi.ki = -2;//(int)(0.03 * 32.0 * 3.0);	// / 2;
 	s->pi.anti_windup = 1;

 	/* Phase branch lock detection */
@@ -92,7 +92,7 @@ void helper_start(struct spll_helper_state *s)
 {
 	/* Set the bias to the upper end of tuning range. This is to ensure that
 	   the HPLL will always lock on positive frequency offset. */
-	s->pi.bias = s->pi.y_max;
+	s->pi.bias = s->pi.y_min;

 	s->p_setpoint = 0;
 	s->p_adder = 0;

--- a/softpll/spll_main.c
+++ b/softpll/spll_main.c
@@ -34,8 +34,8 @@ void mpll_init(struct spll_main_state *s, int id_ref,
 	s->pi.kp = 1100;		// / 2;
 	s->pi.ki = 30;			// / 2;
 #elif defined(CONFIG_WR_NODE)
-	s->pi.kp = 1100;		// / 2;
-	s->pi.ki = 30;			// / 2;
+	s->pi.kp = -1100;		// / 2;
+	s->pi.ki = -30;			// / 2;
 #else
 #error "Please set CONFIG for wr switch or wr node"
 #endif
@@ -159,11 +159,11 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
 		if (s->ld.locked) {
 			if (s->phase_shift_current < s->phase_shift_target) {
 				s->phase_shift_current++;
-				s->adder_ref++;
+				s->adder_ref--;
 			} else if (s->phase_shift_current >
 				   s->phase_shift_target) {
 				s->phase_shift_current--;
-				s->adder_ref--;
+				s->adder_ref++;
 			}
 		}
 		if (ld_update((spll_lock_det_t *)&s->ld, err))

--- a/softpll/spll_ptracker.c
+++ b/softpll/spll_ptracker.c
@@ -57,7 +57,7 @@ int ptrackers_update(struct spll_ptracker_state *ptrackers, int tag,
 	if(!s->enabled)
 		return 0;

-	register int delta = (tag_ref - tag) & ((1 << HPLL_N) - 1);
+	register int delta = (tag - tag_ref) & ((1 << HPLL_N) - 1);
 	register int index = delta >> (HPLL_N - 2);