This has the purpose of making some definitions
public without having to pull in the entire contents of board-state.h
and all the myriad .h files this would #include

ertm14: ensure correct settings of DDS FTW/Level Adjust when the NCO reset is subscribed (see commets)

dev: indicate force-triggered channels as armed so that fine_pulse_gen_is_triggered() can take forced pulses into consideration too

ertm_get_channel_enable returned the logical NOT of the enable flag,
because the out_state byte has an enum of possible values of which ON is
0 and OFF is 2... This patch makes justice to lo/ref channels and gets
the right value in return

It was mysteriously overlooked when implemented

Add API export of this function

This branch implements a separate function to obtain the enable/disable
status of channels.
Reported-by: Saul Novel <saul.novel.gonzalez@cern.ch>

although frequency and sync status are channelno-independent for LO/REF,
the enable/disable status is not. Thus, the channel number validation
must be refactored to filter out bad LO/REF channel numbers *only* in
ertm_get_output_state

Somehow this went overlooked in the design of the API

Greatly increases performance of the Linux control API. More explanation in the comments of uart_link_recv().

More info:
- we had troubles with the temperature stability of the sync signal generator. The LTC6953 seems to be quite picky
  about the jitter of the SYNC singal, furthermore it seems only to support the 'EZ-Sync' mode which does not seem to resynchronize the sync
  request input to the high-speed clock prior to passing it to divider resets (6952 does, to be put in the future board releases).
- reducing the master freq to 500 MHz makes our 'hit' window for the sync rising edge twice as wide
- we don't need 1 GHz neither on the front panel nor on the RF backplane, so not a big loss.

softpll: rename the 'source tracking' mode to 'phase monitor', as it simply monitors the phases of the external (aux clocks) to the local WR clock

ertm14: implement wait for eRTM15 powerup by polling a flag generated by its MMC. Necessary due to uncertainty in the MTCA MCH power sequencing order.

Also added (finally!) the front panel LEDs.

So far the flags are used only to pass the power status of the eRTM15 to the WRCore CPU.
The architecture of MTCA.4 does not ensure both modules will be always powered up simultaneously,
so a little wait for (currently up to 1 min) for the analog board to power up is implemented.