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Software for White Rabbit PTP Core
Commit ef9c7f6a authored by Peter Jansweijer's avatar Peter Jansweijer
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expose LPC_PHY STAT and CTRL

parent 4705a190
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Showing with 13 additions and 1 deletion
include/hw/endpoint_mdio.h
View file @ ef9c7f6a
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : endpoint_mdio.h * File : endpoint_mdio.h
* Author : auto-generated by wbgen2 from pcs_regs.wb * Author : auto-generated by wbgen2 from pcs_regs.wb
* Created : Thu Aug 6 10:27:26 2015 * Created : 08/04/20 12:37:45
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...@@ -14,7 +14,11 @@ ...@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_PCS_REGS_WB #ifndef __WBGEN2_REGDEFS_PCS_REGS_WB
#define __WBGEN2_REGDEFS_PCS_REGS_WB #define __WBGEN2_REGDEFS_PCS_REGS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h> #include <inttypes.h>
#endif
#if defined( __GNUC__) #if defined( __GNUC__)
#define PACKED __attribute__ ((packed)) #define PACKED __attribute__ ((packed))
...@@ -389,6 +393,10 @@ ...@@ -389,6 +393,10 @@
#define MDIO_ECTRL_TX_PRBS_SEL_SHIFT 8 #define MDIO_ECTRL_TX_PRBS_SEL_SHIFT 8
#define MDIO_ECTRL_TX_PRBS_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 3) #define MDIO_ECTRL_TX_PRBS_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define MDIO_ECTRL_TX_PRBS_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 3) #define MDIO_ECTRL_TX_PRBS_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for register: Low phase drift calibration status register */
/* definitions for register: Low phase drift calibration control register */
/* [0x0]: REG MDIO Control Register */ /* [0x0]: REG MDIO Control Register */
#define MDIO_REG_MCR 0x00000000 #define MDIO_REG_MCR 0x00000000
/* [0x4]: REG MDIO Status Register */ /* [0x4]: REG MDIO Status Register */
...@@ -409,4 +417,8 @@ ...@@ -409,4 +417,8 @@
#define MDIO_REG_WR_SPEC 0x00000040 #define MDIO_REG_WR_SPEC 0x00000040
/* [0x44]: REG MDIO Extended Control Register */ /* [0x44]: REG MDIO Extended Control Register */
#define MDIO_REG_ECTRL 0x00000044 #define MDIO_REG_ECTRL 0x00000044
/* [0x48]: REG Low phase drift calibration status register */
#define MDIO_REG_LPC_PHY_STAT 0x00000048
/* [0x4c]: REG Low phase drift calibration control register */
#define MDIO_REG_LPC_PHY_CTRL 0x0000004c
#endif #endif
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