Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
Software for White Rabbit PTP Core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
32
Issues
32
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Software for White Rabbit PTP Core
Commits
ef9c7f6a
Commit
ef9c7f6a
authored
Aug 04, 2020
by
Peter Jansweijer
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
expose LPC_PHY STAT and CTRL
parent
4705a190
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
13 additions
and
1 deletion
+13
-1
endpoint_mdio.h
include/hw/endpoint_mdio.h
+13
-1
No files found.
include/hw/endpoint_mdio.h
View file @
ef9c7f6a
...
...
@@ -3,7 +3,7 @@
* File : endpoint_mdio.h
* Author : auto-generated by wbgen2 from pcs_regs.wb
* Created :
Thu Aug 6 10:27:26 201
5
* Created :
08/04/20 12:37:4
5
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...
...
@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_PCS_REGS_WB
#define __WBGEN2_REGDEFS_PCS_REGS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
...
...
@@ -389,6 +393,10 @@
#define MDIO_ECTRL_TX_PRBS_SEL_SHIFT 8
#define MDIO_ECTRL_TX_PRBS_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define MDIO_ECTRL_TX_PRBS_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for register: Low phase drift calibration status register */
/* definitions for register: Low phase drift calibration control register */
/* [0x0]: REG MDIO Control Register */
#define MDIO_REG_MCR 0x00000000
/* [0x4]: REG MDIO Status Register */
...
...
@@ -409,4 +417,8 @@
#define MDIO_REG_WR_SPEC 0x00000040
/* [0x44]: REG MDIO Extended Control Register */
#define MDIO_REG_ECTRL 0x00000044
/* [0x48]: REG Low phase drift calibration status register */
#define MDIO_REG_LPC_PHY_STAT 0x00000048
/* [0x4c]: REG Low phase drift calibration control register */
#define MDIO_REG_LPC_PHY_CTRL 0x0000004c
#endif
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment