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Commit cf36ad05 authored by Adam Wujek's avatar Adam Wujek
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include: rename hal_port_state to wrc_port_state and remove hal headers 

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Needs ppsi commit:
arch-wrpc: rename hal_port_state to wrc_port_state
Signed-off-by: 's avatarAdam Wujek <adam.wujek@creotech.pl>
parent 588d3de1
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Showing with 16 additions and 504 deletions
include/hal_exports.h
View file @ cf36ad05
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __HAL_EXPORTS_H
#define __HAL_EXPORTS_H
#include <stdint.h>
#define HAL_MAX_PORTS 32
#define WRSW_HAL_SERVER_ADDR "wrsw_hal"
// checks if the calibration unit is idle
#define HEXP_CAL_CMD_CHECK_IDLE 1
// enables/disables transmission of calibration pattern
#define HEXP_CAL_CMD_TX_PATTERN 2
// requests a measurement of TX delta
#define HEXP_CAL_CMD_TX_MEASURE 4
// requests a measurement of RX delta
#define HEXP_CAL_CMD_RX_MEASURE 5
#define HEXP_CAL_RESP_BUSY 1
#define HEXP_CAL_RESP_OK 0
#define HEXP_CAL_RESP_ERROR -1
#define HEXP_LOCK_CMD_START 1
#define HEXP_LOCK_CMD_CHECK 2
#define HEXP_LOCK_CMD_ENABLE_TRACKING 3
#define HEXP_LOCK_STATUS_LOCKED 0
#define HEXP_LOCK_STATUS_BUSY 1
#define HEXP_LOCK_STATUS_NONE 2
#define HEXP_PPSG_CMD_GET 0
#define HEXP_PPSG_CMD_ADJUST_PHASE 1
#define HEXP_PPSG_CMD_ADJUST_SEC 2
#define HEXP_PPSG_CMD_ADJUST_NSEC 3
#define HEXP_PPSG_CMD_POLL 4
#define HEXP_PPSG_CMD_SET_VALID 5
#define HEXP_ON 1
#define HEXP_OFF 0
#define HEXP_FREQ 0
#define HEXP_PHASE 1
/////////////////added by ML//////////
#define HEXP_EXTSRC_CMD_CHECK 0
#define HEXP_EXTSRC_STATUS_LOCKED 0
#define HEXP_LOCK_STATUS_BUSY 1
#define HEXP_EXTSRC_STATUS_NOSRC 2
/////////////////////////////////////
#define HAL_TIMING_MODE_GRAND_MASTER 0
#define HAL_TIMING_MODE_FREE_MASTER 1
#define HAL_TIMING_MODE_BC 2
typedef struct {
char port_name[16];
int pps_valid;
uint32_t current_phase_shift;
int32_t adjust_phase_shift;
int64_t adjust_sec;
int32_t adjust_nsec;
uint64_t current_sec;
uint32_t current_nsec;
} hexp_pps_params_t;
/* Port modes (hexp_port_state_t.mode) */
#define HEXP_PORT_MODE_WR_M_AND_S 4
#define HEXP_PORT_MODE_WR_MASTER 1
#define HEXP_PORT_MODE_WR_SLAVE 2
#define HEXP_PORT_MODE_NON_WR 3
#define FIX_ALPHA_FRACBITS 40
/*
#define HEXP_PORT_TSC_RISING 1
#define HEXP_PORT_TSC_FALLING 2
*/
typedef struct {
int timing_mode; /* Free-running Master/GM/BC */
int locked_port;
} hexp_timing_state_t;
/* Prototypes of functions that call on rpc */
extern int halexp_check_running(void);
extern int halexp_reset_port(const char *port_name);
extern int halexp_calibration_cmd(const char *port_name, int command, int on_off);
extern int halexp_lock_cmd(const char *port_name, int command, int priority);
extern int halexp_pps_cmd(int cmd, hexp_pps_params_t *params);
extern int halexp_get_timing_state(hexp_timing_state_t *state);
/* Export structures, shared by server and client for argument matching */
#ifdef HAL_EXPORT_STRUCTURES
//int halexp_check_running();
struct minipc_pd __rpcdef_check_running = {
.name = "check_running",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_END,
},
};
//int halexp_reset_port(const char *port_name);
struct minipc_pd __rpcdef_reset_port = {
.name = "reset_port",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_END,
},
};
//int halexp_calibration_cmd(const char *port_name, int command, int on_off);
struct minipc_pd __rpcdef_calibration_cmd = {
.name = "calibration_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
};
//int halexp_lock_cmd(const char *port_name, int command, int priority);
struct minipc_pd __rpcdef_lock_cmd = {
.name = "lock_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
};
//int halexp_query_ports(hexp_port_list_t *list);
struct minipc_pd __rpcdef_query_ports = {
.name = "query_ports",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_port_list_t),
.args = {
MINIPC_ARG_END,
},
};
//int halexp_pps_cmd(int cmd, hexp_pps_params_t *params);
struct minipc_pd __rpcdef_pps_cmd = {
.name = "pps_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_pps_params_t),
MINIPC_ARG_END,
},
};
struct minipc_pd __rpcdef_get_timing_state = {
.name = "get_timing_state",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_timing_state_t),
.args = {
MINIPC_ARG_END,
},
};
#endif /* HAL_EXPORT_STRUCTURES */
#endif
include/libwr/hal_shmem.h
View file @ cf36ad05
......@@ -6,82 +6,29 @@
#ifndef __LIBWR_HAL_SHMEM_H__
#define __LIBWR_HAL_SHMEM_H__
#include <hal_exports.h>
#include <libwr/sfp_lib.h>
#include <string.h>
/* Port state machine states */
#define HAL_PORT_STATE_DISABLED 0
#define HAL_PORT_STATE_LINK_DOWN 1
#define HAL_PORT_STATE_UP 2
#define HAL_PORT_STATE_CALIBRATION 3
#define HAL_PORT_STATE_LOCKING 4
#define DEFAULT_T2_PHASE_TRANS 0
#define DEFAULT_T4_PHASE_TRANS 0
/* Port delay calibration parameters */
typedef struct hal_port_calibration {
/* PHY delay measurement parameters for PHYs which require
external calibration (i.e. with the feedback network. */
/* minimum possible delay introduced by the PHY. Expressed as time
(in picoseconds) between the beginning of the symbol on the serial input
and the rising edge of the RX clock at which the deserialized word is
available at the parallel output of the PHY. */
uint32_t phy_rx_min;
/* the same set of parameters, but for the TX path of the PHY */
uint32_t phy_tx_min;
/* Current PHY (clock-to-serial-symbol) TX and RX delays, in ps */
uint32_t delta_tx_phy;
uint32_t delta_rx_phy;
/* bit slide expressed in picos */
uint32_t bitslide_ps;
/* Current board routing delays (between the DDMTD inputs to
the PHY clock inputs/outputs), in picoseconds */
uint32_t delta_tx_board;
uint32_t delta_rx_board;
int delta_tx_ps; /* "delta" of this SFP type WRT calibration type */
int delta_rx_ps;
/* When non-zero: RX path is calibrated (delta_*_rx contain valid values) */
int rx_calibrated;
/* When non-zero: TX path is calibrated */
int tx_calibrated;
struct shw_sfp_caldata sfp;
} hal_port_calibration_t;
/* Internal port state structure */
struct hal_port_state {
/* non-zero: allocated */
int in_use;
/* linux i/f name */
char name[16];
struct wrc_port_state {
/* MAC addr */
uint8_t hw_addr[6];
/* ioctl() hw index */
int hw_index;
/* file descriptor for ioctls() */
int fd;
int hw_addr_auto;
/* port timing mode (HEXP_PORT_MODE_xxxx) */
int mode;
/* port FSM state (HAL_PORT_STATE_xxxx) */
int state;
/* fiber type, used to get alpha for SFP frequency */
int fiber_index;
/* 1: PLL is locked to this port */
int locked;
......@@ -91,7 +38,7 @@ struct hal_port_state {
/* current DMTD loopback phase (ps) and whether is it valid or not */
uint32_t phase_val;
int phase_val_valid;
int tx_cal_pending, rx_cal_pending;
/* locking FSM state */
int lock_state;
......@@ -105,43 +52,6 @@ struct hal_port_state {
/* approximate phase value (on master port) at which RX timestamp (T4)
* counter transistion occurs (picoseconds) */
uint32_t t4_phase_transition;
/* Endpoint's base address */
uint32_t ep_base;
};
struct hal_temp_sensors {
int fpga; /* IC19 */
int pll; /* IC18 */
int psl; /* IC20 Power Supply Left (PSL) */
int psr; /* IC17 Power Supply Right (PSR) */
};
/* This is the overall structure stored in shared memory */
#define HAL_SHMEM_VERSION 7 /* Version 7 because of moving of reading
* temperature treshold values to snmpd */
struct hal_shmem_header {
int nports;
struct hal_port_state *ports;
struct hal_temp_sensors temp;
};
static inline int state_up(int state)
{
return (state != HAL_PORT_STATE_LINK_DOWN
&& state != HAL_PORT_STATE_DISABLED);
}
static inline struct hal_port_state *hal_lookup_port(
struct hal_port_state *ports, int nports,
const char *name)
{
int i;
for (i = 0; i < nports; i++)
if (ports[i].in_use && (!strcmp(name, ports[i].name)))
return ports + i;
return NULL;
}
#endif /* __LIBWR_HAL_SHMEM_H__ */
include/libwr/sfp_lib.h deleted 100644 → 0
View file @ 588d3de1
#ifndef __LIBWR_SHW_SFPLIB_H
#define __LIBWR_SHW_SFPLIB_H
/* note each led contains green and orange part */
#define SFP_LED_WRMODE1 (1 << 0)
#define SFP_LED_WRMODE2 (1 << 1)
#define SFP_LED_SYNCED (1 << 2)
#define SFP_TX_DISABLE (1 << 3)
#define shw_sfp_set_led_synced(num, status) \
shw_sfp_set_generic(num, status, SFP_LED_SYNCED)
#define shw_sfp_set_tx_disable(num, status) \
shw_sfp_set_generic(num, status, SFP_TX_DISABLE)
#define SFP_FLAG_CLASS_DATA (1 << 0)
#define SFP_FLAG_DEVICE_DATA (1 << 1)
#define SFP_FLAG_1GbE (1 << 2) /* SFP is 1GbE */
#define SFP_FLAG_IN_DB (1 << 3) /* SFP is present in data base */
#define SFP_SPEED_1Gb 0x0D /* Speed of SFP in 100MB/s. According to
* SFF-8472.PDF: By convention 1.25 Gb/s
* should be rounded up to 0Dh (13 in
* units of 100 MBd) for Ethernet
* 1000BASE-X. */
#define SFP_SPEED_1Gb_10 0x0A /* Unfortunatelly the above is not always true,
* e.g. Cisco copper SFP (MGBT1) says simply 10 and not 13.*/
#define SFP_SPEED_1Gb_12 0x0C /* Some fiber SFPs say 12 and not 13 */
#define SFP_DIAGNOSTIC_IMPLEMENTED (1 << 6) /* Digital diagnostic monitoring
implemented. "1" for compliance
with SFF-8472 */
#define SFP_ADDR_CHANGE_REQ (1 << 2) /* Bit 2 indicates whether or not it is
necessary for the host to perform an
address change sequence before
accessing information at 2-wire serial
address A2h. */
struct shw_sfp_caldata {
uint32_t flags;
/*
* Part number used to identify it. Serial number because we
* may specify per-specimen delays, but it is not used at this
* point in time
*/
char vendor_name[16];
char part_num[16];
char vendor_serial[16];
/* Callibration data */
double alpha;
int delta_tx_ps; /* "delta" of this SFP type WRT calibration type */
int delta_rx_ps;
/* wavelengths, used to get alpha from fiber type */
int tx_wl;
int rx_wl;
/* and link as a list */
struct shw_sfp_caldata *next;
};
struct shw_sfp_header {
uint8_t id;
uint8_t ext_id;
uint8_t connector;
uint8_t transciever[8];
uint8_t encoding;
uint8_t br_nom;
uint8_t reserved1;
uint8_t length1; /* Link length supported for 9/125 mm fiber (km) */
uint8_t length2; /* Link length supported for 9/125 mm fiber (100m) */
uint8_t length3; /* Link length supported for 50/125 mm fiber (10m) */
uint8_t length4; /* Link length supported for 62.5/125 mm fiber (10m) */
uint8_t length5; /* Link length supported for copper (1m) */
uint8_t length6; /* Link length supported on OM3 (1m) */
uint8_t vendor_name[16];
uint8_t reserved3; /* This is now a field named transceiver */
uint8_t vendor_oui[3];
uint8_t vendor_pn[16];
uint8_t vendor_rev[4];
uint8_t tx_wavelength[2];
uint8_t reserved4;
uint8_t cc_base;
/* extended ID fields start here */
uint8_t options[2];
uint8_t br_max;
uint8_t br_min;
uint8_t vendor_serial[16];
uint8_t date_code[8];
uint8_t diagnostic_monitoring_type;
uint8_t enhanced_options;
uint8_t sff_8472_compliance;
uint8_t cc_ext;
} __attribute__ ((packed));
struct shw_sfp_dom {
/* Treshold values, 0 - 55 */
uint8_t temp_high_alarm[2];
uint8_t temp_low_alarm[2];
uint8_t temp_high_warn[2];
uint8_t temp_low_warn[2];
uint8_t volt_high_alarm[2];
uint8_t volt_low_alarm[2];
uint8_t volt_high_warn[2];
uint8_t volt_low_warn[2];
uint8_t bias_high_alarm[2];
uint8_t bias_low_alarm[2];
uint8_t bias_high_warn[2];
uint8_t bias_low_warn[2];
uint8_t tx_pow_high_alarm[2];
uint8_t tx_pow_low_alarm[2];
uint8_t tx_pow_high_warn[2];
uint8_t tx_pow_low_warn[2];
uint8_t rx_pow_high_alarm[2];
uint8_t rx_pow_log_alarm[2];
uint8_t rx_power_high_warn[2];
uint8_t rx_power_low_warn[2];
uint8_t unalloc0[16];
/* Calibration data, 56-91 */
uint8_t cal_rx_pwr4[4];
uint8_t cal_rx_pwr3[4];
uint8_t cal_rx_pwr2[4];
uint8_t cal_rx_pwr1[4];
uint8_t cal_rx_pwr0[4];
uint8_t cal_tx_i_slope[2];
uint8_t cal_tx_i_offset[2];
uint8_t cal_tx_pow_slope[2];
uint8_t cal_tx_pow_offset[2];
uint8_t cal_T_slope[2];
uint8_t cal_T_offset[2];
uint8_t cal_V_slope[2];
uint8_t cal_V_offset[2];
/* Unallocated and checksum, 92-95 */
uint8_t cal_unalloc[3];
uint8_t CC_DMI;
/* Real Time Diagnostics, 96-111 */
uint8_t temp[2];
uint8_t vcc[2];
uint8_t tx_bias[2];
uint8_t tx_pow[2];
uint8_t rx_pow[2];
uint8_t rtd_unalloc0[4];
uint8_t OSCB;
uint8_t rtd_unalloc1;
/* Alarms and Warnings, 112 - 117 */
uint8_t alw[6];
/* Extended Module Control/Status bytes 118 - 119 */
uint8_t emcsb[2];
/* Vendor locations 120 - 127 */
uint8_t vendor_locations[8];
/* User data 128 - 247 */
uint8_t dom_user[120];
/* Vendor specific control function locations 248 - 255 */
uint8_t vendor_functions[8];
} __attribute__ ((packed));
/* Public API */
/*
* Scan all ports for plugged in SFP's. The return value is a bitmask
* of all the ports with detected SFP's (bits 0-17 are valid).
*/
uint32_t shw_sfp_module_scan(void);
/* Set/get the 4 GPIO's connected to PCA9554's for a particular SFP */
void shw_sfp_gpio_set(int num, uint8_t state);
uint8_t shw_sfp_gpio_get(int num);
static inline void shw_sfp_set_generic(int num, int status, int type)
{
uint8_t state;
state = shw_sfp_gpio_get(num);
if (status)
state |= type;
else
state &= ~type;
shw_sfp_gpio_set(num, state);
}
/* Load the db from dot-config to internal structures */
int shw_sfp_read_db(void);
/* Read and verify the header all at once. returns -1 on failure */
int shw_sfp_read_verify_header(int num, struct shw_sfp_header *head);
/* Read the SFP diagnostics page */
int shw_sfp_read_dom(int num, struct shw_sfp_dom *dom);
/* Update the SFP diagnostics page */
int shw_sfp_update_dom(int num, struct shw_sfp_dom *dom);
/* Decode and print the SFP real time diagnostics */
void shw_sfp_print_dom(struct shw_sfp_dom * dom);
/* Dump the SFP diagnostics page in hex */
void shw_sfp_dom_dump(struct shw_sfp_dom * dom);
/* return NULL if no data found */
struct shw_sfp_caldata *shw_sfp_get_cal_data(int num,
struct shw_sfp_header *head);
#endif /* __LIBWR_SHW_SFPLIB_H */
include/ptpd_netif.h
View file @ cf36ad05
......@@ -111,8 +111,8 @@ void ptpd_netif_linearize_rx_timestamp(struct wr_timestamp *ts,
int clock_period);
void ptpd_netif_set_phase_transition(uint32_t phase);
struct hal_port_state;
int wrpc_get_port_state(struct hal_port_state *port,
struct wrc_port_state;
int wrpc_get_port_state(struct wrc_port_state *port,
const char *port_name /* unused */);
#endif /* __PTPD_NETIF_H */
lib/net.c
View file @ cf36ad05
......@@ -49,7 +49,7 @@ struct wrpc_socket *ptpd_netif_create_socket(struct wrpc_socket *sock,
int udp_or_raw, int udpport)
{
int i;
struct hal_port_state pstate;
struct wrc_port_state pstate;
/* Look for the first available socket. */
for (i = 0; i < ARRAY_SIZE(socks); i++)
......
lib/ppsi-wrappers.c
View file @ cf36ad05
......@@ -18,11 +18,11 @@
#include <board.h>
struct wrs_shm_head *ppsi_head;
void *ppsi_head;
/* Following code from ptp-noposix/libposix/freestanding-wrapper.c */
static int read_phase_val(struct hal_port_state *port)
static int read_phase_val(struct wrc_port_state *port)
{
int32_t dmtd_phase;
......@@ -39,34 +39,21 @@ static int read_phase_val(struct hal_port_state *port)
extern uint32_t cal_phase_transition;
int wrpc_get_port_state(struct hal_port_state *port, const char *port_name)
int wrpc_get_port_state(struct wrc_port_state *port, const char *port_name)
{
if (wrc_ptp_get_mode() == WRC_MODE_SLAVE)
port->mode = HEXP_PORT_MODE_WR_SLAVE;
else
port->mode = HEXP_PORT_MODE_WR_MASTER;
/* all deltas are added anyway */
ep_get_deltas(&wrc_endpoint_dev, &port->calib.sfp.delta_tx_ps,
&port->calib.sfp.delta_rx_ps);
ep_get_deltas(&wrc_endpoint_dev, &port->calib.delta_tx_ps,
&port->calib.delta_rx_ps);
/* get the bitslide */
port->calib.bitslide_ps = ep_get_bitslide(&wrc_endpoint_dev);
port->calib.delta_tx_phy = 0;
port->calib.delta_rx_phy = 0;
port->calib.delta_tx_board = 0;
port->calib.delta_rx_board = 0;
read_phase_val(port);
port->state = ep_link_up(&wrc_endpoint_dev, NULL);
port->calib.tx_calibrated = 1;
port->calib.rx_calibrated = 1;
port->locked = spll_check_lock(0);
/* port->lock_priority = 0;*/
/*spll_get_phase_shift(0, NULL, (int32_t *)&port->phase_setpoint);*/
port->clock_period = REF_CLOCK_PERIOD_PS;
port->t2_phase_transition = cal_phase_transition;
port->t4_phase_transition = cal_phase_transition;
ep_get_mac_addr(&wrc_endpoint_dev, port->hw_addr);
port->hw_index = 0;
return 0;
}
......
monitor/monitor_ppsi.c
View file @ cf36ad05
......@@ -422,7 +422,7 @@ void print_main_description(void)
void print_main_data(void)
{
struct hal_port_state state;
struct wrc_port_state state;
int tx, rx;
int leap_sec, tmp;
uint64_t sec;
......@@ -853,7 +853,7 @@ void print_servo_data(struct pp_instance *ppi)
int wrc_log_stats(void)
{
#if 0
struct hal_port_state state;
struct wrc_port_state state;
int tx, rx;
struct spll_aux_clock_status aux_stat;
uint64_t sec;
......@@ -945,7 +945,7 @@ int wrc_log_stats(void)
int wrc_wr_diags(void)
{
#if 0
struct hal_port_state ps;
struct wrc_port_state ps;
static uint32_t last_jiffies;
int tx, rx;
uint64_t sec;
......
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