Skip to content

S
Software for White Rabbit PTP Core
Commit 7104e58f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

softpll: increase N factor (frequency offset) to 15 to give more headroom to the… 

softpll: increase N factor (frequency offset) to 15 to give more headroom to the helper oscillator and prevent un-locks
parent 4ded48b2
Hide whitespace changes
Inline Side-by-side
Showing with 15 additions and 11 deletions
include/spll_defs.h
View file @ 7104e58f
......@@ -28,7 +28,7 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
/* Helper PLL N divider (2**(-N) is the frequency offset). Must be big enough
to offer reasonable PLL bandwidth, and small enough so the offset frequency fits
within the tuning range of the helper oscillator. */
#define HPLL_N 14
#define HPLL_N 15
/* Fractional bits in PI controller coefficients */
#define PI_FRACBITS 12
......
softpll/softpll_ng.c
View file @ 7104e58f
......@@ -320,7 +320,7 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
SPLL->RCER = 0;
SPLL->ECCR = 0;
SPLL->OCCR = 0;
SPLL->DEGLITCH_THR = 1000;
SPLL->DEGLITCH_THR = 2000;
PPSG->ESCR = 0;
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_CNT_RST | PPSG_CR_PWIDTH_W(PPS_WIDTH);
......
softpll/spll_helper.c
View file @ 7104e58f
......@@ -25,13 +25,13 @@ void helper_init(struct spll_helper_state *s, int ref_channel)
/* Phase branch PI controller */
s->pi.y_min = 5;
s->pi.y_max = (1 << DAC_BITS) - 5;
s->pi.kp = 150;//(int)(0.3 * 32.0 * 16.0); // / 2;
s->pi.ki = 2;//(int)(0.03 * 32.0 * 3.0); // / 2;
s->pi.kp = 150;
s->pi.ki = 4;
s->pi.anti_windup = 1;
/* Phase branch lock detection */
s->ld.threshold = 200;
s->ld.lock_samples = 10000;
s->ld.lock_samples = 5000;
s->ld.delock_samples = 100;
s->ref_src = ref_channel;
s->delock_count = 0;
......
softpll/spll_main.c
View file @ 7104e58f
......@@ -29,12 +29,12 @@ void mpll_init(struct spll_main_state *s, int id_ref,
s->pi.anti_windup = 1;
s->pi.bias = 65000;
s->pi.kp = 1100; // / 2;
s->pi.ki = 30; // / 2;
s->pi.ki = 60; // / 2;
s->delock_count = 0;
/* Freqency branch lock detection */
s->ld.threshold = 1200;
s->ld.lock_samples = 1000;
s->ld.lock_samples = 500;
s->ld.delock_samples = 100;
s->id_ref = id_ref;
s->id_out = id_out;
......@@ -174,13 +174,17 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
}
if (s->ld.locked) {
int delta = abs(s->phase_shift_current - s->phase_shift_target);
if(delta > 2)
delta = 2;
if (s->phase_shift_current < s->phase_shift_target) {
s->phase_shift_current++;
s->adder_ref++;
s->phase_shift_current += delta;
s->adder_ref += delta;
} else if (s->phase_shift_current >
s->phase_shift_target) {
s->phase_shift_current--;
s->adder_ref--;
s->phase_shift_current -= delta;
s->adder_ref -= delta;
}
}
if (ld_update((spll_lock_det_t *)&s->ld, err))
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment