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Software for White Rabbit PTP Core
Commit 4a549f5c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wip

parent 496615c6
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Showing with 272 additions and 154 deletions
boards/afcz/board.c
View file @ 4a549f5c
......@@ -413,6 +413,8 @@ static void wr_si57x_interface_init( struct wr_si57x_interface_device *dev, uint
}
// fixme: factor out all this code to a common file (used by sis83k, afcz, ertm)
static int calc_apr(int meas_min, int meas_max, int f_center )
{
// apr_min is in PPM
......@@ -442,37 +444,54 @@ static int calc_apr(int meas_min, int meas_max, int f_center )
return ppm_lo < ppm_hi ? ppm_lo : ppm_hi;
}
static void check_vco_freq( int cm_channel, int cm_ref, void (*dac_setter)(int ))
static int gen_rnd( )
{
int f_min, f_max;
int tune_min = 0;
static const uint32_t lcg_m = 1103515245;
static const uint32_t lcg_i = 12345;
static uint32_t seed = 0;
seed *= lcg_m;
seed += lcg_i;
seed &= 0x7fffffffUL;
return seed;
}
static int measure_vcxo_freq( int cm_channel, int cm_ref, int gate_freq, int n_steps, uint32_t expected_freq, void (*dac_setter)(int), int *apr, uint32_t *base_freq )
{
int f_min = 0, f_max = 0;
int tune_min = 3000;
int tune_max = 65535;
int tune_step = 5000;
int tune_step = 1; //(tune_max-tune_min) / n_steps;
wb_cm_configure( &board.clk_mon, cm_ref, 5, 1000000 );
wb_cm_configure( &board.clk_mon, cm_ref, 5, gate_freq );
wb_cm_set_ref_frequency( &board.clk_mon, CPU_CLOCK );
int tune = tune_min;
for(;;)
{
dac_setter( tune );
timer_delay_ms(1);
dac_setter( tune + (gen_rnd() % 3000) - 1500);
timer_delay_ms(5);
wb_cm_restart( &board.clk_mon );
while( ! (wb_cm_read( &board.clk_mon ) & ( 1<< cm_channel) ) );
while( ! (wb_cm_read( &board.clk_mon ) & ( 1<< cm_channel) ) )
{
dac_setter( tune + (gen_rnd() % 3000) - 1500);
timer_delay_ms(5);
}
int f = board.clk_mon.freqs[ cm_channel ];
if( tune == tune_min )
f_min = f;
else if ( tune == tune_max )
f_max = f;
if(tune == tune_max)
break;
pp_printf("Tune: %d f = %d Hz (deltaF = %d Hz)\n", tune, f, f - 62500000 );
board_dbg("Tune: %d f = %d Hz (deltaF = %d Hz)\n", tune, f, f - expected_freq );
tune += tune_step;
if( tune > tune_max )
......@@ -482,10 +501,21 @@ static void check_vco_freq( int cm_channel, int cm_ref, void (*dac_setter)(int )
dac_setter( 32768 );
timer_delay(1);
pp_printf("VCO ch %d: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", cm_channel, f_min, f_max, calc_apr(f_min, f_max, 62500000) );
int l_apr = calc_apr(f_min, f_max, 62500000);
if( apr )
*apr = l_apr;
if( base_freq )
*base_freq = (f_min + f_max) / 2;
board_dbg("VCO ch %d: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", cm_channel, f_min, f_max, l_apr );
return 0;
}
static void set_dmtd_dac( int value )
{
spll_set_dac( -1, value );
......@@ -493,9 +523,24 @@ static void set_dmtd_dac( int value )
static void set_main_dac( int value )
{
//pp_printf("smaind %d\n", value );
spll_set_dac( 0, value );
}
int afcz_check_clocks()
{
//check_vco_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_RX, set_dmtd_dac );
//check_vco_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_RX, set_main_dac );
board_dbg("Check REF VCXO (Si570)\n");
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_RX, 10000000, 10, 62500000, set_main_dac, NULL, NULL );
board_dbg("Check DMTD VCXO\n");
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_RX, 100000, 10, 62500000, set_dmtd_dac, NULL, NULL );
return 0;
}
const struct gpio_pin pin_rtm_4sfp_led_orange = { &board.gpio_rtm_main.gpio, 3 };
const struct gpio_pin pin_rtm_4sfp_i2c_reset_n = { &board.gpio_rtm_main.gpio, 5 };
const struct gpio_pin pin_rtm_4sfp_i2c_enable_n = { &board.gpio_rtm_main.gpio, 6 };
......@@ -629,6 +674,8 @@ int wrc_board_early_init()
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_FPGA_CLK3_OUT, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_FPGA_CLK_GTX_CUST2_OUT, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_FPGA_FMC2_CLK2_BIDIR_OUT, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_configure_io ( &board.clk_mux, 10, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_commit_configuration ( &board.clk_mux );
wb_cm_init( &board.clk_mon, BASE_CLOCK_MONITOR, 6 );
......@@ -675,6 +722,7 @@ int wrc_board_early_init()
#define AFCZ_CLOCK_MON_TIMEOUT_MS 4000
#if 0
int afcz_check_clocks()
{
wb_cm_configure( &board.clk_mon, AFCZ_CM_CHANNEL_CLK_SYS, 5, 10000000 );
......@@ -697,11 +745,11 @@ int afcz_check_clocks()
pp_printf("Checking clocks: RX clock freq = %d Hz\n", board.clk_mon.freqs[ AFCZ_CM_CHANNEL_CLK_RX ]);
pp_printf("Checking DDMTD and REF clock frequencies:\n");
check_vco_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_RX, set_dmtd_dac );
check_vco_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_RX, set_main_dac );
// afcz_check_clocks();
return 0;
}
#endif
int wrc_board_init()
{
......@@ -718,7 +766,7 @@ int wrc_board_init()
&pin_sysc_spi_sclk, 10 );
spi_wrc_flash.rd_falling_edge = 1;
int retries = 100;
int retries = 1000000;
uint32_t id;
flash_entry_points[0] = 0x1f00000;
......
boards/afcz/board.h
View file @ 4a549f5c
......@@ -22,7 +22,7 @@
#define BASE_SOFTPLL 0x20200
#define BASE_PPS_GEN 0x20300
#define BASE_AUXWB 0x20700
#define BASE_AUXWB 0x28000
#define BASE_SI57X_INTERFACE (BASE_AUXWB + 0x80)
#define BASE_CLOCK_MONITOR (BASE_AUXWB + 0xc0)
#define BASE_WR_ENDPOINT_BTRAIN (BASE_AUXWB + 0x00)
......
boards/ertm14/board.c
View file @ 4a549f5c
......@@ -36,6 +36,9 @@
#include "dev/pps_gen.h"
#include "dev/console.h"
#include "dev/endpoint.h"
#include "lib/ertm14-uart-link.h"
#include "softpll_ng.h"
#include "storage.h"
#include "wrc_ptp.h"
......@@ -66,104 +69,104 @@
#define ERTM14_IUART_MSG_PING 8
struct ertm14_board board;
static struct ertm14_board_state ertm14_configs[ ERTM14_MAX_CONFIGS ];
static struct ertm14_board_state *ertm14_current_state;
static struct gpio_pin pin_pll_main_cs_n = { &board.gpio_aux, 0 };
static struct gpio_pin pin_pll_main_sdi = { &board.gpio_aux, 1 };
static struct gpio_pin pin_pll_main_sdo = { &board.gpio_aux, 2 };
static struct gpio_pin pin_pll_main_sclk = { &board.gpio_aux, 3 };
static struct gpio_pin pin_pll_main_reset = { &board.gpio_aux, 4 };
static struct gpio_pin pin_pll_main_lock = { &board.gpio_aux, 5 };
static struct gpio_pin pin_pll_ext_cs_n = { &board.gpio_aux, 6 };
static struct gpio_pin pin_pll_ext_sdi = { &board.gpio_aux, 7 };
static struct gpio_pin pin_pll_ext_sdo = { &board.gpio_aux, 8 };
static struct gpio_pin pin_pll_ext_sclk = { &board.gpio_aux, 9 };
static struct gpio_pin pin_pll_ext_reset = { &board.gpio_aux, 10 };
static struct gpio_pin pin_pll_ext_lock = { &board.gpio_aux, 11 };
static struct gpio_pin pin_mac_addr_scl = { &board.gpio_aux, 13 };
static struct gpio_pin pin_mac_addr_sda = { &board.gpio_aux, 12 };
static struct gpio_pin pin_main_xo_en_n = { &board.gpio_aux, 14 };
static struct gpio_pin pin_ltc6950_sclk = { &board.gpio_aux, 15 };
static struct gpio_pin pin_ltc6950_sdi = { &board.gpio_aux, 16 };
static struct gpio_pin pin_ltc6950_sdo = { &board.gpio_aux, 17 };
static struct gpio_pin pin_ltc6950_ce_gen = { &board.gpio_aux, 18 };
static struct gpio_pin pin_ltc6950_ce_distr = { &board.gpio_aux, 19 };
static struct gpio_pin pin_ltc6950_sync = { &board.gpio_aux, 20 };
static struct gpio_pin pin_ad9910_lo_sdio = { &board.gpio_aux, 4+21 };
static struct gpio_pin pin_ad9910_lo_sclk = { &board.gpio_aux, 5+21 };
static struct gpio_pin pin_ad9910_lo_reset = { &board.gpio_aux, 6+21 };
static struct gpio_pin pin_ad9910_lo_io_update = { &board.gpio_aux, 3+21 };
struct ertm14_board_state ertm14_configs[ ERTM14_MAX_CONFIGS ];
struct ertm14_board_state *ertm14_current_state;
struct gpio_pin pin_pll_main_cs_n = { &board.gpio_aux, 0 };
struct gpio_pin pin_pll_main_sdi = { &board.gpio_aux, 1 };
struct gpio_pin pin_pll_main_sdo = { &board.gpio_aux, 2 };
struct gpio_pin pin_pll_main_sclk = { &board.gpio_aux, 3 };
struct gpio_pin pin_pll_main_reset = { &board.gpio_aux, 4 };
struct gpio_pin pin_pll_main_lock = { &board.gpio_aux, 5 };
struct gpio_pin pin_pll_ext_cs_n = { &board.gpio_aux, 6 };
struct gpio_pin pin_pll_ext_sdi = { &board.gpio_aux, 7 };
struct gpio_pin pin_pll_ext_sdo = { &board.gpio_aux, 8 };
struct gpio_pin pin_pll_ext_sclk = { &board.gpio_aux, 9 };
struct gpio_pin pin_pll_ext_reset = { &board.gpio_aux, 10 };
struct gpio_pin pin_pll_ext_lock = { &board.gpio_aux, 11 };
struct gpio_pin pin_mac_addr_scl = { &board.gpio_aux, 13 };
struct gpio_pin pin_mac_addr_sda = { &board.gpio_aux, 12 };
struct gpio_pin pin_main_xo_en_n = { &board.gpio_aux, 14 };
struct gpio_pin pin_ltc6950_sclk = { &board.gpio_aux, 15 };
struct gpio_pin pin_ltc6950_sdi = { &board.gpio_aux, 16 };
struct gpio_pin pin_ltc6950_sdo = { &board.gpio_aux, 17 };
struct gpio_pin pin_ltc6950_ce_gen = { &board.gpio_aux, 18 };
struct gpio_pin pin_ltc6950_ce_distr = { &board.gpio_aux, 19 };
struct gpio_pin pin_ltc6950_sync = { &board.gpio_aux, 20 };
struct gpio_pin pin_ad9910_lo_sdio = { &board.gpio_aux, 4+21 };
struct gpio_pin pin_ad9910_lo_sclk = { &board.gpio_aux, 5+21 };
struct gpio_pin pin_ad9910_lo_reset = { &board.gpio_aux, 6+21 };
struct gpio_pin pin_ad9910_lo_io_update = { &board.gpio_aux, 3+21 };
const struct gpio_pin pin_ad9910_lo_sync_smp_err = { &board.gpio_aux, 5+21 };
static struct gpio_pin pin_ad9910_ref_sdio = { &board.gpio_aux, 4+28 };
static struct gpio_pin pin_ad9910_ref_sclk = { &board.gpio_aux, 5+28 };
static struct gpio_pin pin_ad9910_ref_reset = { &board.gpio_aux, 6+28 };
static struct gpio_pin pin_ad9910_ref_io_update = { &board.gpio_aux, 3+28 };
struct gpio_pin pin_ad9910_ref_sdio = { &board.gpio_aux, 4+28 };
struct gpio_pin pin_ad9910_ref_sclk = { &board.gpio_aux, 5+28 };
struct gpio_pin pin_ad9910_ref_reset = { &board.gpio_aux, 6+28 };
struct gpio_pin pin_ad9910_ref_io_update = { &board.gpio_aux, 3+28 };
const struct gpio_pin pin_ad9910_ref_sync_smp_err = { &board.gpio_aux, 5+28 };
static struct gpio_pin pin_ocxo_override = { &board.gpio_aux, 48 };
static struct gpio_pin pin_ocxo_cs_n = { &board.gpio_aux, 51 };
static struct gpio_pin pin_ocxo_sclk = { &board.gpio_aux, 50 };
static struct gpio_pin pin_ocxo_data = { &board.gpio_aux, 49 };
struct gpio_pin pin_ocxo_override = { &board.gpio_aux, 48 };
struct gpio_pin pin_ocxo_cs_n = { &board.gpio_aux, 51 };
struct gpio_pin pin_ocxo_sclk = { &board.gpio_aux, 50 };
struct gpio_pin pin_ocxo_data = { &board.gpio_aux, 49 };
static struct gpio_pin pin_pwrmon_adc_cs_n = { &board.gpio_aux, 52 };
static struct gpio_pin pin_pwrmon_adc_dout = { &board.gpio_aux, 46 };
static struct gpio_pin pin_pwrmon_adc_din = { &board.gpio_aux, 47 };
static struct gpio_pin pin_pwrmon_adc_sclk = { &board.gpio_aux, 45 };
struct gpio_pin pin_pwrmon_adc_cs_n = { &board.gpio_aux, 52 };
struct gpio_pin pin_pwrmon_adc_dout = { &board.gpio_aux, 46 };
struct gpio_pin pin_pwrmon_adc_din = { &board.gpio_aux, 47 };
struct gpio_pin pin_pwrmon_adc_sclk = { &board.gpio_aux, 45 };
static struct gpio_pin pin_sys_clk_sel_stb = { &board.gpio_aux, 61 };
static struct gpio_pin pin_sys_clk_sel_next = { &board.gpio_aux, 62 };
struct gpio_pin pin_sys_clk_sel_stb = { &board.gpio_aux, 61 };
struct gpio_pin pin_sys_clk_sel_next = { &board.gpio_aux, 62 };
static struct gpio_pin pin_pps_out_mode0 = { &board.gpio_aux, 63 };
static struct gpio_pin pin_pps_out_mode1 = { &board.gpio_aux, 64 };
static struct gpio_pin pin_pps_out_mode2 = { &board.gpio_aux, 65 };
struct gpio_pin pin_pps_out_mode0 = { &board.gpio_aux, 63 };
struct gpio_pin pin_pps_out_mode1 = { &board.gpio_aux, 64 };
struct gpio_pin pin_pps_out_mode2 = { &board.gpio_aux, 65 };
static struct gpio_pin pin_led_sync_green = { &board.gpio_aux, 69 };
static struct gpio_pin pin_led_sync_red = { &board.gpio_aux, 70 };
struct gpio_pin pin_led_sync_green = { &board.gpio_aux, 69 };
struct gpio_pin pin_led_sync_red = { &board.gpio_aux, 70 };
static struct gpio_pin pin_ertm15_leds_ser = { &board.gpio_aux, 66 };
static struct gpio_pin pin_ertm15_leds_updtclk = { &board.gpio_aux, 67 };
static struct gpio_pin pin_ertm15_leds_shftclk = { &board.gpio_aux, 68 };
struct gpio_pin pin_ertm15_leds_ser = { &board.gpio_aux, 66 };
struct gpio_pin pin_ertm15_leds_updtclk = { &board.gpio_aux, 67 };
struct gpio_pin pin_ertm15_leds_shftclk = { &board.gpio_aux, 68 };
// a/b/lo/ref, red->green
static struct gpio_pin pin_ertm15_led_clka_red = { &board.gpio_ertm15_leds, 0 };
static struct gpio_pin pin_ertm15_led_clka_green = { &board.gpio_ertm15_leds, 1 };
static struct gpio_pin pin_ertm15_led_clkb_red = { &board.gpio_ertm15_leds, 2 };
static struct gpio_pin pin_ertm15_led_clkb_green = { &board.gpio_ertm15_leds, 3 };
static struct gpio_pin pin_ertm15_led_lo_red = { &board.gpio_ertm15_leds, 4 };
static struct gpio_pin pin_ertm15_led_lo_green = { &board.gpio_ertm15_leds, 5 };
static struct gpio_pin pin_ertm15_led_ref_red = { &board.gpio_ertm15_leds, 6 };
static struct gpio_pin pin_ertm15_led_ref_green = { &board.gpio_ertm15_leds, 7 };
static struct gpio_pin pin_ertm15_clkab_mosi = { &board.gpio_aux, 57 };
static struct gpio_pin pin_ertm15_clkab_miso = { &board.gpio_aux, 57 };
static struct gpio_pin pin_ertm15_clkab_sck = { &board.gpio_aux, 58 };
static struct gpio_pin pin_ertm15_clka_cs_n = { &board.gpio_aux, 59 };
static struct gpio_pin pin_ertm15_clkb_cs_n = { &board.gpio_aux, 60 };
static struct ad95xx_config pll_ext_10mhz_config =
struct gpio_pin pin_ertm15_led_clka_red = { &board.gpio_ertm15_leds, 0 };
struct gpio_pin pin_ertm15_led_clka_green = { &board.gpio_ertm15_leds, 1 };
struct gpio_pin pin_ertm15_led_clkb_red = { &board.gpio_ertm15_leds, 2 };
struct gpio_pin pin_ertm15_led_clkb_green = { &board.gpio_ertm15_leds, 3 };
struct gpio_pin pin_ertm15_led_lo_red = { &board.gpio_ertm15_leds, 4 };
struct gpio_pin pin_ertm15_led_lo_green = { &board.gpio_ertm15_leds, 5 };
struct gpio_pin pin_ertm15_led_ref_red = { &board.gpio_ertm15_leds, 6 };
struct gpio_pin pin_ertm15_led_ref_green = { &board.gpio_ertm15_leds, 7 };
struct gpio_pin pin_ertm15_clkab_mosi = { &board.gpio_aux, 57 };
struct gpio_pin pin_ertm15_clkab_miso = { &board.gpio_aux, 57 };
struct gpio_pin pin_ertm15_clkab_sck = { &board.gpio_aux, 58 };
struct gpio_pin pin_ertm15_clka_cs_n = { &board.gpio_aux, 59 };
struct gpio_pin pin_ertm15_clkb_cs_n = { &board.gpio_aux, 60 };
struct ad95xx_config pll_ext_10mhz_config =
#include "configs/ertm_14_pll_ext_10mhz.h"
static struct ad95xx_config pll_main_dot050_config =
struct ad95xx_config pll_main_dot050_config =
#include "configs/ertm_14_pll_main_dot050_config.h"
static struct ad95xx_config pll_main_ocxo_config =
struct ad95xx_config pll_main_ocxo_config =
#include "configs/ertm_14_pll_ocxo_config.h"
static struct ltc695x_config pll_ertm15_bootstrap_config =
struct ltc695x_config pll_ertm15_bootstrap_config =
#include "configs/ertm_15_ltc6950_config_rev2.h"
static struct ltc695x_config clkab_ertm15_bootstrap_config =
struct ltc695x_config clkab_ertm15_bootstrap_config =
#include "configs/ertm_15_ltc6953_bootstrap_config.h"
static spll_gain_schedule_t spll_main_ocxo_gain_sched;
spll_gain_schedule_t spll_main_ocxo_gain_sched;
#define ERTM14_BIST_LTC6950 0
#define ERTM14_BIST_MAC_EEPROM 1
......@@ -198,6 +201,7 @@ static struct bist_stage ertm_bist[] = {
{ERTM14_BIST_DDS_REF, "DDS comm (REF)", 1},
{0, NULL}};
void bist_checkpoint( struct bist_stage *bist, int id, int channel, int pass )
{
int i;
......@@ -222,9 +226,9 @@ void bist_init( struct bist_stage *bist )
int bist_summary( struct bist_stage *bist )
{
int i;
int n_ok, n_errors;
int n_ok = 0, n_errors = 0;
pp_printf("Built-in Self Test Summary\n------------------------------\n");
pp_printf("Id | Test name | Channel | Status ");
pp_printf("Id | Test name | Channel | Status \n");
for(i = 0; bist[i].name; i++ )
{
......@@ -233,11 +237,36 @@ int bist_summary( struct bist_stage *bist )
for( ch = 0; ch < s->n_channels; ch++ )
{
pp_printf("%-2d | %-30s | ", i + 1, bist[i].name);
}
pp_printf("%-3d | %-31s | ", i + 1, bist[i].name);
if( s->n_channels > 1 )
pp_printf("%-02d | ", ch );
else
pp_printf("- | ");
int stat = s->status >> (ch * 2);
if( !( stat & BIST_STATUS_DONE ) )
pp_printf("Not ran");
else if (stat & BIST_STATUS_ERROR)
{
pp_printf("ERROR");
n_errors++;
}
else
{
pp_printf("OK");
n_ok++;
}
pp_printf("\n");
}
}
if( n_errors )
pp_printf("--------------------------------\nBIST FAILED with %d ERRORS!\n\n\n", n_errors );
else
pp_printf("BIST PASSED.\n");
return n_errors > 0 ? -1 : 0;
}
......@@ -630,6 +659,19 @@ static void iuart_14_poll(void)
}
}
static int control_uart_poll(void)
{
struct uart_packet pkt;
if( uart_link_recv( &board.control_uart, &pkt ) > 0 )
{
/*... dispatch */
}
return 0;
}
static void ertm14_clock_monitor_init(void)
{
wb_cm_init(&board.ertm14_cmon, BASE_CLOCK_MONITOR, 5);
......@@ -826,7 +868,7 @@ static int calc_apr(int meas_min, int meas_max, int f_center )
static int measure_vcxo_freq( int cm_channel, int cm_ref, int gate_freq, int n_steps, uint32_t expected_freq, void (*dac_setter)(int), int *apr, uint32_t *base_freq )
{
int f_min, f_max;
int f_min = 0, f_max = 0;
int tune_min = 0;
int tune_max = 65535;
int tune_step = (tune_max-tune_min) / n_steps;
......@@ -843,14 +885,14 @@ static int measure_vcxo_freq( int cm_channel, int cm_ref, int gate_freq, int n_s
timer_delay_ms(1);
wb_cm_restart( &board.ertm14_cmon );
while( ! (wb_cm_read( &board.ertm14_cmon ) & ( 1<< cm_channel) ) );
int f = board.ertm14_cmon.freqs[ cm_channel ];
if( tune == tune_min )
f_min = f;
else if ( tune == tune_max )
f_max = f;
if(tune == tune_max)
break;
......@@ -919,6 +961,7 @@ int ertm15_check_oscillators()
measure_vcxo_freq( ERTM14_CMON_CLK_REF, ERTM14_CMON_CLK_DMTD, 10000000, 1, 62500000, set_main_dac, NULL, NULL );
board_dbg("Check DMTD VCXO\n");
measure_vcxo_freq( ERTM14_CMON_CLK_DMTD, ERTM14_CMON_CLK_REF, 100000, 10, 62500000, set_dmtd_dac, NULL, NULL );
return 0;
}
// initializes the eRTM15 LTC6950 PLL & OCXO
......@@ -934,7 +977,7 @@ int ertm15_pll_init(void)
return -1;
}
bist_checkpoint(&ertm_bist, ERTM14_BIST_LTC6950, 0, id == LTC6950_ID_VALUE);
bist_checkpoint( ertm_bist, ERTM14_BIST_LTC6950, 0, id == LTC6950_ID_VALUE);
// load default 'bootstrap' config and check what is the OCXO frequency
ltc695x_configure(&board.ltc6950_pll, &pll_ertm15_bootstrap_config);
......@@ -946,7 +989,7 @@ int ertm15_pll_init(void)
ltc695x_write(&board.ltc6950_pll, 0x15, 50); // RDIVOUT = 0, output div = 50
ltc695x_write(&board.ltc6950_pll, 0x0a, 10); // N divider = 10 (VCO @ 1GHz, PFD @ 10 MHz)
board.mode |= ERTM14_MODE_OCXO_100MHZ;
return 0;
}
static struct clkab_output_map_entry *clkab_find_map_entry( int clka_or_clkb, int output )
......@@ -1020,8 +1063,8 @@ int ertm14_init_clkab_distribution()
int result_a = ltc695x_configure( &board.dev_clka_distr, &clkab_ertm15_bootstrap_config );
int result_b = ltc695x_configure( &board.dev_clkb_distr, &clkab_ertm15_bootstrap_config );
bist_checkpoint( &ertm_bist, ERTM14_BIST_CLKA, 0, (id_a == LTC6953_EXPECTED_ID) && !result_a );
bist_checkpoint( &ertm_bist, ERTM14_BIST_CLKB, 0, (id_b == LTC6953_EXPECTED_ID) && !result_b );
bist_checkpoint( ertm_bist, ERTM14_BIST_CLKA, 0, (id_a == LTC6953_EXPECTED_ID) && !result_a );
bist_checkpoint( ertm_bist, ERTM14_BIST_CLKB, 0, (id_b == LTC6953_EXPECTED_ID) && !result_b );
if( id_a != LTC6953_EXPECTED_ID || id_b != LTC6953_EXPECTED_ID )
return -ENODEV;
......@@ -1038,6 +1081,7 @@ int ertm14_init_clkab_distribution()
// (so that any clock output is possible)
fine_pulse_gen_force_pulse( &board.dds_sync_dev, ERTM14_PLL_SYNC_CLKA );
fine_pulse_gen_force_pulse( &board.dds_sync_dev, ERTM14_PLL_SYNC_CLKB );
return 0;
}
int ertm14_init_ref_clock_distribution(void)
......@@ -1045,8 +1089,8 @@ int ertm14_init_ref_clock_distribution(void)
int main_stat = ad951x_init(&board.ad9516_main, &board.spi_pll_main, &pin_pll_main_reset, &pin_pll_main_lock);
int ext_stat = ad951x_init(&board.ad9516_ext, &board.spi_pll_ext, &pin_pll_ext_reset, &pin_pll_ext_lock);
bist_checkpoint( &ertm_bist, ERTM14_BIST_AD951X_MAIN, 0, main_stat == 0 );
bist_checkpoint( &ertm_bist, ERTM14_BIST_AD951X_EXT, 0, ext_stat == 0 );
bist_checkpoint( ertm_bist, ERTM14_BIST_AD951X_MAIN, 0, main_stat == 0 );
bist_checkpoint( ertm_bist, ERTM14_BIST_AD951X_EXT, 0, ext_stat == 0 );
if( main_stat < 0 )
{
......@@ -1071,6 +1115,7 @@ int ertm14_init_ref_clock_distribution(void)
ad951x_configure(&board.ad9516_main, &pll_main_ocxo_config);
// ad951x_configure(&board.ad9516_ext, &pll_ext_10mhz_config);
}
return 0;
}
int ertm15_init_dds(void)
......@@ -1087,8 +1132,12 @@ int ertm15_init_dds(void)
// initialize DDS synchronizer unit
ertm14_dds_sync_init();
ad9910_probe( &board.dds_ad9910_ref, &board.spi_ad9910_ref, ertm14_dds_trigger_ioupdate );
ad9910_probe( &board.dds_ad9910_lo, &board.spi_ad9910_lo, ertm14_dds_trigger_ioupdate );
int probe_ref = ad9910_probe( &board.dds_ad9910_ref, &board.spi_ad9910_ref, ertm14_dds_trigger_ioupdate );
int probe_lo = ad9910_probe( &board.dds_ad9910_lo, &board.spi_ad9910_lo, ertm14_dds_trigger_ioupdate );
bist_checkpoint( ertm_bist, ERTM14_BIST_DDS_LO, 0, probe_lo == 0 );
bist_checkpoint( ertm_bist, ERTM14_BIST_DDS_REF, 0, probe_ref == 0 );
return 0;
}
int ertm14_init_mac_eeprom(void)
......@@ -1104,7 +1153,7 @@ int ertm14_init_mac_eeprom(void)
int err = m24aa025_read_mac( &board.m24_mac_ids[0], mac );
//m24aa025_read_mac( &board.m24_mac_ids[1], mac );
bist_checkpoint( &ertm_bist, ERTM14_BIST_MAC_EEPROM, 0, !err );
bist_checkpoint( ertm_bist, ERTM14_BIST_MAC_EEPROM, 0, !err );
if( err < 0 )
return err;
......@@ -1304,15 +1353,14 @@ int ertm14_low_level_init(void)
/* Initialize the IUART which is responsible for the communication with the MMC.
Fixme: below is IUART14 which talks to the MMC on eRTM14. If eRTM15 is present, we need another IUART device. */
board_dbg("Init IUART14\n");
iuart_init_bare( &board.iuart_14, BASE_IUART_14, 115200 );
//ertm15_rf_distr_self_test( &board.rf_distr ;
board_dbg("Init Control UART Link\n");
uart_link_create_wrpc( &board.control_uart, 921600 );
board_dbg("Init RF transceiver\n");
wr_rf_frame_transceiver_create( &board.rf_xcvr, BASE_ERTM14_RF_FRAME_TRANSCEIVER );
board_dbg("eRTM14/15 early init done\n");
ertm_init_complete = 1;
......@@ -1369,6 +1417,7 @@ int ertm14_apply_config(int config_id)
board_dbg("Apply_config: %d\n", config_id );
ertm14_current_state = &ertm14_configs[config_id];
event_post ( WRC_ERTM14_EVENT_APPLY_NEW_CONFIG );
return 0;
}
int ertm14_get_current_config_id()
......@@ -1494,6 +1543,8 @@ int wrc_board_early_init()
static int32_t flash_entry_points[64];
int i;
bist_init( ertm_bist );
/* initialize SPI flash */
bb_spi_create( &spi_wrc_flash,
&pin_sysc_spi_ncs,
......@@ -1531,11 +1582,15 @@ int wrc_board_early_init()
ep_enable( &wrc_endpoint_dev, 1, 1);
timer_delay_ms(200);
return ertm14_low_level_init();
int ll = ertm14_low_level_init();
bist_summary( ertm_bist );
return ll;
}
extern int phy_calibration_poll();
extern void phy_calibration_init();
extern int phy_calibration_poll(void);
extern void phy_calibration_init(void);
int wrc_board_init()
{
......@@ -1544,7 +1599,8 @@ int wrc_board_init()
evth_dds_nco_sync = event_listener_create();
evth_config_update_listener = event_listener_create();
wrc_task_create( "iuart14", NULL, iuart_14_poll );
//wrc_task_create( "iuart14", NULL, iuart_14_poll );
wrc_task_create( "control-uart", NULL, control_uart_poll );
wrc_task_create( "rf-nco-sync", ertm14_dds_nco_sync_init, ertm14_dds_nco_sync_task );
wrc_task_create( "ertm-config", ertm14_config_update_init, ertm14_config_update_task );
wrc_task_create( "phy-cal", phy_calibration_init, phy_calibration_poll );
......
boards/ertm14/board.h
View file @ 4a549f5c
......@@ -20,6 +20,7 @@
#include "dev/spi_flash.h"
#include "dev/bb_i2c.h"
#include "dev/iuart.h"
#include "lib/ertm14-uart-link.h"
#include "rf_frame_transceiver.h"
#define BOARD_HAS_CUSTOM_NETWORK_INIT 1
......@@ -146,6 +147,11 @@ extern unsigned char *BASE_EP;
#define WRC_ERTM14_EVENT_APPLY_NEW_CONFIG (WRC_EVENT_PRIVATE_START+0)
#define WRC_ERTM14_EVENT_RECONFIGURED (WRC_EVENT_PRIVATE_START+1)
// UART Protocol packet types
#define ERTM14_UART_PTYPE_PING 1
#define ERTM14_UART_PTYPE_SNMP_REQ 2
#define ERTM14_UART_PTYPE_SNMP_RESP 3
struct ertm14_board
{
struct gpio_device gpio_aux;
......@@ -178,6 +184,7 @@ struct ertm14_board
struct iuart_device iuart_14;
struct wr_rf_frame_transceiver_device rf_xcvr;
struct gpio_device gpio_ertm15_leds;
struct uart_link control_uart;
int mode;
int dds_resync_count;
......
dev/console.c
View file @ 4a549f5c
......@@ -92,7 +92,7 @@ static int con_uart_put_string(struct console_device* dev, const char *s)
if( dev->flags & CONSOLE_FLAGS_MODE_BINARY )
return 0;
while ( c = *s++ )
while ( (c = *s++) != 0 )
{
if( (dev->flags & CONSOLE_FLAGS_INSERT_CRLF) && c == '\n')
suart_write_byte(&priv->uart_dev, '\r');
......@@ -106,8 +106,8 @@ static int con_uart_put_string(struct console_device* dev, const char *s)
static int con_uart_getc(struct console_device* dev)
{
//if( dev->flags & CONSOLE_FLAGS_MODE_BINARY )
//return 0;
if( dev->flags & CONSOLE_FLAGS_MODE_BINARY )
return 0;
return con_rx_internal( dev );
}
......@@ -204,6 +204,7 @@ static inline int rbuf_full(struct ring_buffer *buf)
static inline int rbuf_purge(struct ring_buffer *buf)
{
buf->head = buf->tail = buf->count = 0;
return 0;
}
......@@ -211,7 +212,7 @@ static int con_ipmi_put_string(struct console_device* dev, const char *s)
{
struct console_ipmi_priv_data* priv = (struct console_ipmi_priv_data*) dev->priv;
int c, n = 0;
while( c = *s++ )
while( (c = *s++) != 0 )
{
rbuf_put( &priv->tx_buf, c );
n++;
......@@ -234,7 +235,6 @@ int console_ipmi_process_request(struct console_device* dev, uint8_t *req, int
struct console_ipmi_priv_data* priv = (struct console_ipmi_priv_data*) dev->priv;
int i;
int cnt = priv->tx_buf.count;
for(i = 0; i < size; i++ )
{
......@@ -259,13 +259,13 @@ int console_ipmi_process_request(struct console_device* dev, uint8_t *req, int
return i;
}
void console_ipmi_init( )
void console_ipmi_init( void )
{
console_ipmi_dev.priv = &console_ipmi_priv;
console_ipmi_dev.get_char = con_ipmi_getc;
console_ipmi_dev.put_string = con_ipmi_put_string;
rbuf_init(&console_ipmi_priv.rx_buf, IPMI_CON_RX_BUF_SIZE, &console_ipmi_priv.rx_buf_mem);
rbuf_init(&console_ipmi_priv.tx_buf, IPMI_CON_TX_BUF_SIZE, &console_ipmi_priv.tx_buf_mem);
rbuf_init(&console_ipmi_priv.rx_buf, IPMI_CON_RX_BUF_SIZE, console_ipmi_priv.rx_buf_mem);
rbuf_init(&console_ipmi_priv.tx_buf, IPMI_CON_TX_BUF_SIZE, console_ipmi_priv.tx_buf_mem);
console_register_device( &console_ipmi_dev );
}
......@@ -351,44 +351,37 @@ int console_get_mode( struct console_device *dev )
return dev->flags & ( CONSOLE_FLAGS_MODE_BINARY | CONSOLE_FLAGS_MODE_TTY );
}
int console_binary_send( struct console_device *dev, void *buf, int size )
int console_binary_send_byte( struct console_device *dev, uint8_t b )
{
struct console_uart_priv_data* priv = (struct console_uart_priv_data*) dev->priv;
if( dev->flags & CONSOLE_FLAGS_MODE_TTY )
return 0;
int has_fifo = suart_is_fifo_supported( &priv->uart_dev );
if( !has_fifo )
return -ENODEV;
// fixme: FIFO threshold check?
uint8_t *ptr = (uint8_t*) buf;
int i;
for(i = 0; i< size; i++)
suart_write_byte( &priv->uart_dev, ptr[i] );
suart_write_byte( &priv->uart_dev, b );
return size;
return 0;
}
int console_binary_recv( struct console_device *dev, void *buf, int size )
int console_binary_recv_byte( struct console_device *dev )
{
struct console_uart_priv_data* priv = (struct console_uart_priv_data*) dev->priv;
if( dev->flags & CONSOLE_FLAGS_MODE_TTY )
return -1;
int has_fifo = suart_is_fifo_supported( &priv->uart_dev );
if( !has_fifo )
return -ENODEV;
int rx_count = suart_poll( &priv->uart_dev );
if( rx_count < size )
return -EAGAIN;
uint8_t *ptr = (uint8_t*) buf;
int i;
for(i = 0; i< size; i++)
ptr[i] = suart_read_byte(&priv->uart_dev );
int rx_byte = con_rx_internal( dev );
return size;
return rx_byte;
}
dev/ltc695x.c
View file @ 4a549f5c
......@@ -37,6 +37,8 @@ uint8_t ltc695x_read(struct ltc695x_device *dev, uint32_t reg) {
bb_spi_write( dev->bus, (reg << 1) | 1, 8);
rv = bb_spi_read(dev->bus, 8);
bb_spi_cs(dev->bus, 0);
pp_printf("REad %x %x\n", reg, rv );
return rv;
}
......@@ -56,6 +58,8 @@ int ltc695x_configure(struct ltc695x_device *dev, struct ltc695x_config* cfg)
for(i = 0; i < cfg->n_regs; i++) {
ltc695x_write(dev, cfg->regs[i].addr, cfg->regs[i].value);
}
return 0;
}
#define LTC6953_PD_NORMAL (0)
......@@ -87,7 +91,7 @@ int ltc6953_set_pdown( struct ltc695x_device *dev, int out, int pd )
r &= ~( 0x3 << shift );
r |= pd << shift;
dev_dbg("ltc6953 out %d [addr %x mask %x r %x] PD = %d\n", out, reg, shift, r, pd );
//dev_dbg("ltc6953 out %d [addr %x mask %x r %x] PD = %d\n", out, reg, shift, r, pd );
ltc695x_write(dev, reg, r );
return 0;
......@@ -125,7 +129,6 @@ int ltc6953_configure_output( struct ltc695x_device *dev, int output, int divide
dev_dbg("ltc6953 r%02x = %02x\n", base+0, or0 );
dev_dbg("ltc6953 r%02x = %02x\n", base+1, or1 );
ltc695x_write( dev, base + 0, or0 );
ltc695x_write( dev, base + 1, or1 );
......
dev/minic.c
View file @ 4a549f5c
......@@ -213,6 +213,8 @@ int minic_rx_frame(struct wr_ethhdr *hdr, uint8_t * payload, uint32_t buf_size,
/* Increment Rx counter for statistics */
minic.rx_count++;
pp_printf("RX %d\n", payload_size );
if (minic_readl(MINIC_REG_MCR) & MINIC_MCR_RX_FULL)
pp_printf("Warning: Minic Rx fifo full, expect wrong frames\n");
......
include/dev/console.h
View file @ 4a549f5c
......@@ -21,8 +21,7 @@ struct console_device {
int flags;
};
extern struct console_device *console;
extern struct console_device console_uart_dev;
void console_set_device( struct console_device *dev );
void console_uart_write_bytes( uint8_t *buf, int count );
......@@ -33,8 +32,8 @@ int console_getc(void);
void console_force_mode( struct console_device *dev, int mode );
int console_get_mode( struct console_device *dev );
int console_binary_send( struct console_device *dev, void *buff, int size );
int console_binary_recv( struct console_device *dev, void *buff, int size );
int console_binary_send_byte( struct console_device *dev, uint8_t b );
int console_binary_recv_byte( struct console_device *dev );
#ifdef CONFIG_IPMI_CONSOLE
int console_ipmi_process_request(struct console_device* dev, uint8_t *req, int size, uint8_t *rsp, int rsp_size );
......
lib/lib.mk
View file @ 4a549f5c
......@@ -13,3 +13,4 @@ obj-$(CONFIG_SYSLOG) += lib/syslog.o
obj-$(CONFIG_LATENCY_PROBE) += lib/latency.o
obj-$(CONFIG_SNMP) += lib/snmp.o
obj-$(CONFIG_LLDP) += lib/lldp.o
obj-$(CONFIG_TARGET_ERTM14) += lib/ertm14-uart-link.o
\ No newline at end of file
lib/net.c
View file @ 4a549f5c
......@@ -231,6 +231,8 @@ int ptpd_netif_recvfrom(struct wrpc_socket *s, struct wr_sockaddr *from, void *d
if (!q->n)
return 0;
pp_printf("QNotEmpty\n");
q->n--;
q->avail += wrap_copy_in(&size, q, 2, 0);
......@@ -341,6 +343,8 @@ int net_bh_poll(void)
return 0;
}
pp_printf("F1\n");
/* Prepare for IP/UDP checks */
if (payload[IP_VERSION] == 0x45 && payload[IP_PROTOCOL] == 17)
port = payload[UDP_DPORT] << 8 | payload[UDP_DPORT + 1];
......@@ -351,8 +355,11 @@ int net_bh_poll(void)
s = socks[i];
if (!s)
continue;
pp_printf("check sock %p\n", s);
pp_printf("check e %x %x\n", hdr.ethtype , s->bind_addr.ethertype);
if (hdr.ethtype != s->bind_addr.ethertype)
continue;
if (!port && !s->bind_addr.udpport)
raws = s; /* match with raw socket */
if (port && s->bind_addr.udpport == port)
......@@ -367,6 +374,8 @@ int net_bh_poll(void)
return 1;
}
pp_printf("F2\n");
q = &s->queue;
q_required =
sizeof(struct wr_ethhdr) + recvd + sizeof(struct hw_timestamp) + 2;
......@@ -378,6 +387,8 @@ int net_bh_poll(void)
return 1;
}
pp_printf("F3\n");
size = recvd;
q->avail -= wrap_copy_out(q, &size, 2);
......
softpll/softpll_ng.c
View file @ 4a549f5c
......@@ -20,8 +20,6 @@
#include "irq.h"
#define pll_verbose pp_printf
#ifdef CONFIG_SPLL_FIFO_LOG
struct spll_fifo_log fifo_log[FIFO_LOG_LEN];
#define HAS_FIFO_LOG 1
......
wrc_main.c
View file @ 4a549f5c
......@@ -132,7 +132,7 @@ static int wrc_check_link(void)
int rv = 0;
if (!prev_state && state) {
wrc_verbose("Link up.\n");
main_dbg("Link up.\n");
event_post( WRC_EVENT_LINK_UP );
gen_gpio_out(&pin_sysc_led_link, 1);
sfp_match(0);
......@@ -140,7 +140,7 @@ static int wrc_check_link(void)
link_status = NETIF_LINK_WENT_UP;
rv = 1;
} else if (prev_state && !state) {
wrc_verbose("Link down.\n");
main_dbg("Link down.\n");
prev_timing_ok = 0;
event_post( WRC_EVENT_LINK_DOWN );
gen_gpio_out(&pin_sysc_led_link, 0);
......
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