temp commit (AFCZ hacks)

496615c6 · Tomasz Wlostowski · ae9a049d · 496615c6 · 496615c6 · 496615c6
Commit 496615c6 authored Oct 30, 2020 by Tomasz Wlostowski
9 changed files
--- a/arch/lm32/ram-wrs.ld
+++ b/arch/lm32/ram-wrs.ld
@@ -31,10 +31,10 @@ ENTRY(_start)

 MEMORY
 {
-    ram   : ORIGIN = 0x0000, LENGTH = 0x6800
-    stats : ORIGIN = 0x6800, LENGTH = 0x0800
-    mbox  : ORIGIN = 0x7000, LENGTH = 0x1000
-    stack : ORIGIN = 0x8000, LENGTH = 0x8000
+    ram   : ORIGIN = 0x0000, LENGTH = 0x9800
+    stats : ORIGIN = 0x9800, LENGTH = 0x0800
+    mbox  : ORIGIN = 0xa000, LENGTH = 0x1000
+    stack : ORIGIN = 0xb000, LENGTH = 0x3000
 }

 SECTIONS

--- a/boards/afcz/board.c
+++ b/boards/afcz/board.c
--- a/boards/afcz/board.h
+++ b/boards/afcz/board.h
-/*
- * This work is part of the White Rabbit project
- *
- * Released according to the GNU GPL, version 2 or any later version.
- */
-#ifndef __BOARD_WRC_H
-#define __BOARD_WRC_H
-/*
- * This is meant to be automatically included by the Makefile,
- * when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
- */
-
-#define BOARD_HAS_CUSTOM_NETWORK_INIT 1
-
-/* Fixed base addresses */
-
-#define BASE_UART                   0x20500
-#define BASE_SYSCON                 0x20400
-#define BASE_WR_ENDPOINT_MAIN       0x20100
-#define BASE_MINIC                  0x20000
-#define BASE_ONEWIRE                0x20600
-#define BASE_SOFTPLL 0x20200
-#define BASE_PPS_GEN 0x20300
-
-#define BASE_AUXWB 0x20700
-#define BASE_SI57X_INTERFACE (BASE_AUXWB + 0x80)
-#define BASE_CLOCK_MONITOR (BASE_AUXWB + 0xc0)
-#define BASE_WR_ENDPOINT_BTRAIN     (BASE_AUXWB + 0x00)
-
-#define AFCZ_CM_CHANNEL_CLK_PCB 0
-#define AFCZ_CM_CHANNEL_CLK_SYS 3
-#define AFCZ_CM_CHANNEL_CLK_RX 2
-#define AFCZ_CM_CHANNEL_CLK_REF 1
-#define AFCZ_CM_CHANNEL_CLK_DMTD 5
-
-#define AFCZ_IC33_CLK_SI570_1_IN 13
-#define AFCZ_IC33_CLK_SI570_2_IN 15
-#define AFCZ_IC33_FPGA_CLK3_OUT 9
-#define AFCZ_IC33_FPGA_CLK_GTX_CUST2_OUT 8
-
-#define AFCZ_I2C_MUX_CHANNEL_SI570 2
-#define AFCZ_I2C_MUX_CHANNEL_RTM 7
-
-#define AFCZ_I2C_ADDR_MAC_EEPROM 0x59
-
-#define AFCZ_I2C_EEPROM_MAC_OFFSET 0x9a
-
-#define RTM_4SFP_MUX_SFP0 0
-#define RTM_4SFP_MUX_SFP1 1
-#define RTM_4SFP_MUX_SFP2 2
-#define RTM_4SFP_MUX_SFP3 3
-#define RTM_4SFP_MUX_SFP4 4
-#define RTM_4SFP_MUX_SFP5 5
-#define RTM_4SFP_MUX_SFP6 6
-
-
-
-/* Board-specific parameters */
-#define TICS_PER_SECOND 1000
-
-/* WR Core system/CPU clock frequency in Hz */
-#define CPU_CLOCK 62500000ULL
-
-/* WR Reference clock period (picoseconds) and frequency (Hz) */
-#define REF_CLOCK_PERIOD_PS 16000
-#define REF_CLOCK_FREQ_HZ 62500000
-
-#define NS_PER_CLOCK 16
-
-/* Baud rate of the builtin UART (does not apply to the VUART) */
-#define UART_BAUDRATE 115200ULL
-
-/* Maximum number of simultaneously created sockets */
-#define NET_MAX_SOCKETS 12
-
-/* Socket buffer size, determines the max. RX packet size */
-#define NET_MAX_SKBUF_SIZE 512
-
-/* Number of auxillary clock channels - usually equal to the number of FMCs */
-#define NUM_AUX_CLOCKS 1
-
-int board_init(void);
-int board_update(void);
-
-/* spll parameter that are board-specific */
-#define BOARD_DIVIDE_DMTD_CLOCKS	0
-#define BOARD_MAX_CHAN_REF		1
-#define BOARD_MAX_CHAN_AUX		2
-#define BOARD_MAX_PTRACKERS		1
-
-#undef CONFIG_DISALLOW_LONG_DIVISION
-
-#define BOARD_MAX_CONSOLE_DEVICES 1
-
-#define CONSOLE_UART_BAUDRATE 115200
-
-#define SDB_ADDRESS 0x30000
-
-#define FMC_EEPROM_ADR 0x50
-
-#define SDBFS_REC 5
- 
-
-void sdb_find_devices(void);
-void sdb_print_devices(void);
-
-#endif /* __BOARD_WRC_H */
+/*
+ * This work is part of the White Rabbit project
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+#ifndef __BOARD_WRC_H
+#define __BOARD_WRC_H
+/*
+ * This is meant to be automatically included by the Makefile,
+ * when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
+ */
+
+#define BOARD_HAS_CUSTOM_NETWORK_INIT 1
+
+/* Fixed base addresses */
+
+#define BASE_UART                   0x20500
+#define BASE_SYSCON                 0x20400
+#define BASE_WR_ENDPOINT_MAIN       0x20100
+#define BASE_MINIC                  0x20000
+#define BASE_ONEWIRE                0x20600
+#define BASE_SOFTPLL 0x20200
+#define BASE_PPS_GEN 0x20300
+
+#define BASE_AUXWB 0x20700
+#define BASE_SI57X_INTERFACE (BASE_AUXWB + 0x80)
+#define BASE_CLOCK_MONITOR (BASE_AUXWB + 0xc0)
+#define BASE_WR_ENDPOINT_BTRAIN     (BASE_AUXWB + 0x00)
+
+#define AFCZ_CM_CHANNEL_CLK_PCB 0
+#define AFCZ_CM_CHANNEL_CLK_SYS 3
+#define AFCZ_CM_CHANNEL_CLK_RX 2
+#define AFCZ_CM_CHANNEL_CLK_REF 1
+#define AFCZ_CM_CHANNEL_CLK_DMTD 5
+
+#define AFCZ_IC33_CLK_SI570_1_IN 13
+#define AFCZ_IC33_CLK_SI570_2_IN 15
+#define AFCZ_IC33_FPGA_CLK3_OUT 9
+#define AFCZ_IC33_FPGA_CLK_GTX_CUST2_OUT 8
+#define AFCZ_IC33_FPGA_FMC2_CLK2_BIDIR_OUT 14
+
+#define AFCZ_I2C_MUX_CHANNEL_SI570 2
+#define AFCZ_I2C_MUX_CHANNEL_RTM 7
+
+#define AFCZ_I2C_ADDR_MAC_EEPROM 0x59
+
+#define AFCZ_I2C_EEPROM_MAC_OFFSET 0x9a
+
+#define RTM_4SFP_MUX_SFP0 0
+#define RTM_4SFP_MUX_SFP1 1
+#define RTM_4SFP_MUX_SFP2 2
+#define RTM_4SFP_MUX_SFP3 3
+#define RTM_4SFP_MUX_SFP4 4
+#define RTM_4SFP_MUX_SFP5 5
+#define RTM_4SFP_MUX_SFP6 6
+
+
+
+/* Board-specific parameters */
+#define TICS_PER_SECOND 1000
+
+/* WR Core system/CPU clock frequency in Hz */
+#define CPU_CLOCK 62500000ULL
+
+/* WR Reference clock period (picoseconds) and frequency (Hz) */
+#define REF_CLOCK_PERIOD_PS 16000
+#define REF_CLOCK_FREQ_HZ 62500000
+
+#define NS_PER_CLOCK 16
+
+/* Baud rate of the builtin UART (does not apply to the VUART) */
+#define UART_BAUDRATE 115200ULL
+
+/* Maximum number of simultaneously created sockets */
+#define NET_MAX_SOCKETS 12
+
+/* Socket buffer size, determines the max. RX packet size */
+#define NET_MAX_SKBUF_SIZE 512
+
+/* Number of auxillary clock channels - usually equal to the number of FMCs */
+#define NUM_AUX_CLOCKS 1
+
+int board_init(void);
+int board_update(void);
+
+/* spll parameter that are board-specific */
+#define BOARD_DIVIDE_DMTD_CLOCKS	0
+#define BOARD_MAX_CHAN_REF		1
+#define BOARD_MAX_CHAN_AUX		2
+#define BOARD_MAX_PTRACKERS		1
+
+#undef CONFIG_DISALLOW_LONG_DIVISION
+
+#define BOARD_MAX_CONSOLE_DEVICES 1
+
+#define CONSOLE_UART_BAUDRATE 115200
+
+#define SDB_ADDRESS 0x30000
+
+#define FMC_EEPROM_ADR 0x50
+
+#define SDBFS_REC 5
+ 
+
+void sdb_find_devices(void);
+void sdb_print_devices(void);
+
+#endif /* __BOARD_WRC_H */
--- a/boards/ertm14/ertm15_rf_distr.c
+++ b/boards/ertm14/ertm15_rf_distr.c
@@ -146,7 +146,7 @@ void ertm15_rf_distr_init( struct ertm15_rf_distribution_device *dev, struct ad7

 static int convert_power( int adc_value )
 {
-    //pp_printf("ADCV %d\n", adc_value );
+    pp_printf("ADCV %d\n", adc_value );

    float adc_voltage = (float) adc_value / 4096.0 * 2.5;
    float rf_power = 10.0 * log( adc_voltage / 2.0 ) / log( 10.0 ) + 15.0; // 2V = 0 dBm, compensate for 15 dB attenuator

--- a/dev/simple_uart.c
+++ b/dev/simple_uart.c
@@ -62,10 +62,10 @@ int suart_get_rx_fifo_count( struct simple_uart_device *dev )

 int suart_poll(struct simple_uart_device *dev)
 {
-	if( suart_is_fifo_supported( dev ) )
+	/*if( suart_is_fifo_supported( dev ) )
 	{
 		return suart_get_rx_fifo_count( dev );
-	}
+	}*/
 	
 	return readl( dev->base + UART_REG_SR) & UART_SR_RX_RDY ? 1 : 0;
 }

--- a/softpll/softpll_ng.c
+++ b/softpll/softpll_ng.c
@@ -20,6 +20,8 @@

 #include "irq.h"

+#define pll_verbose pp_printf
+
 #ifdef CONFIG_SPLL_FIFO_LOG
  struct spll_fifo_log fifo_log[FIFO_LOG_LEN];
  #define HAS_FIFO_LOG 1
@@ -397,6 +399,7 @@ void spll_init(int mode, int slave_ref_channel, int flags)
 	if(mode == SPLL_MODE_DISABLED)
 		return;

+	softpll.mpll.gain_sched = NULL;
 	
 	SPLL->EIC_IER = 1;
 	SPLL->OCER |= 1;

--- a/softpll/spll_external.c
+++ b/softpll/spll_external.c
@@ -119,7 +119,7 @@ int external_align_fsm(volatile struct spll_external_state *s)
 				SPLL->ECCR &= (~SPLL_ECCR_EXT_REF_PLLRST);
 				timer_delay(10);
 				ljd_ad9516_stat = ljd_ad9516_init();
-				f_ext = spll_measure_frequency(SPLL_OSC_EXT);
+				f_ext = 10000000; //spll_measure_frequency(SPLL_OSC_EXT);
 				if (!ljd_ad9516_stat && (f_ext > 9999000) && (f_ext < 10001000)) {
 					s->align_state = ALIGN_STATE_WAIT_PLOCK;
 					pp_printf("External AD9516 locked\n");

--- a/softpll/spll_main.c
+++ b/softpll/spll_main.c
@@ -260,7 +260,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
 	return SPLL_LOCKING;
 }

-#ifdef CONFIG_PPSI /* use __div64_32 from ppsi library to save libgcc memory */
+// #ifdef CONFIG_PPSI /* use __div64_32 from ppsi library to save libgcc memory */
 static int32_t from_picos(int32_t ps)
 {
 	extern uint32_t __div64_32(uint64_t *n, uint32_t base);
@@ -275,13 +275,13 @@ static int32_t from_picos(int32_t ps)
 	__div64_32(&ups, CLOCK_PERIOD_PICOSECONDS);
 	return -ups;
 }
-#else /* previous implementation: ptp-noposix has no __div64_32 available */
-static int32_t from_picos(int32_t ps)
-{
-	return (int32_t) ((int64_t) ps * (int64_t) (1 << HPLL_N) /
-			  (int64_t) CLOCK_PERIOD_PICOSECONDS);
-}
-#endif
+//#else /* previous implementation: ptp-noposix has no __div64_32 available */
+//static int32_t from_picos(int32_t ps)
+//{
+//	return (int32_t) ((int64_t) ps * (int64_t) (1 << HPLL_N) /
+//			  (int64_t) CLOCK_PERIOD_PICOSECONDS);
+//}
+//#endif

 int mpll_set_phase_shift(struct spll_main_state *s,
 				int desired_shift_ps)

--- a/wrc_main.c
+++ b/wrc_main.c
@@ -136,7 +136,7 @@ static int wrc_check_link(void)
 		event_post( WRC_EVENT_LINK_UP );
 		gen_gpio_out(&pin_sysc_led_link, 1);
 		sfp_match(0);
-		wrc_ptp_start();
+		//wrc_ptp_start();
 		link_status = NETIF_LINK_WENT_UP;
 		rv = 1;
 	} else if (prev_state && !state) {
@@ -148,7 +148,7 @@ static int wrc_check_link(void)
 		wrc_ptp_stop();
 		rv = 1;
 		/* special case */
-		spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, SPLL_FLAG_ALIGN_PPS);
+		//spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, SPLL_FLAG_ALIGN_PPS);
 		shw_pps_gen_enable_output(0);

 	} else