Skip to content
Snippets Groups Projects
Commit cfe1c9e7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files

updated register layouts to match the new PPS gen, SoftPLL, Endpoint and Minic

parent 152df8aa
No related merge requests found
Hide whitespace changes
Inline Side-by-side
include/hw/endpoint_regs.h
+ 166
− 71
View file @ cfe1c9e7
......@@ -3,7 +3,7 @@
* File : endpoint_regs.h
* Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
* Created : Wed Apr 6 22:46:02 2011
* Created : Sun Oct 30 00:20:59 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -42,11 +42,23 @@
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Transmit path enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Receive path enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Feature present: VLAN tagging in reg: Endpoint Control Register */
#define EP_ECR_FEAT_VLAN WBGEN2_GEN_MASK(24, 1)
/* definitions for field: Feature present: DDMTD phase measurement in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DMTD WBGEN2_GEN_MASK(25, 1)
/* definitions for field: Feature present: IEEE1588 timestamper in reg: Endpoint Control Register */
#define EP_ECR_FEAT_PTP WBGEN2_GEN_MASK(26, 1)
/* definitions for field: Feature present: DPI packet classifier in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DPI WBGEN2_GEN_MASK(27, 1)
/* definitions for register: Timestamping Control Register */
......@@ -73,29 +85,96 @@
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for field: RX keep CRC in reg: RX Deframer Control Register */
#define EP_RFCR_KEEP_CRC WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX Fiter HP Priorities in reg: RX Deframer Control Register */
#define EP_RFCR_HPAP_MASK WBGEN2_GEN_MASK(4, 8)
#define EP_RFCR_HPAP_SHIFT 4
#define EP_RFCR_HPAP_W(value) WBGEN2_GEN_WRITE(value, 4, 8)
#define EP_RFCR_HPAP_R(reg) WBGEN2_GEN_READ(reg, 4, 8)
/* definitions for field: Maximum receive unit (MRU) in reg: RX Deframer Control Register */
#define EP_RFCR_MRU_MASK WBGEN2_GEN_MASK(12, 14)
#define EP_RFCR_MRU_SHIFT 12
#define EP_RFCR_MRU_W(value) WBGEN2_GEN_WRITE(value, 12, 14)
#define EP_RFCR_MRU_R(reg) WBGEN2_GEN_READ(reg, 12, 14)
/* definitions for register: VLAN control register 0 */
/* definitions for field: RX 802.1q port mode in reg: VLAN control register 0 */
#define EP_VCR0_QMODE_MASK WBGEN2_GEN_MASK(0, 2)
#define EP_VCR0_QMODE_SHIFT 0
#define EP_VCR0_QMODE_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define EP_VCR0_QMODE_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Force 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_FIX_PRIO WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port-assigned 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define EP_VCR0_PRIO_VAL_SHIFT 4
#define EP_VCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define EP_VCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Port-assigned VID in reg: VLAN control register 0 */
#define EP_VCR0_PVID_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_VCR0_PVID_SHIFT 16
#define EP_VCR0_PVID_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_VCR0_PVID_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: VLAN Control Register 1 */
/* definitions for field: Egress untagged set bitmap VID in reg: VLAN Control Register 1 */
#define EP_VCR1_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_VCR1_VID_SHIFT 0
#define EP_VCR1_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_VCR1_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Egress untagged set bitmap value in reg: VLAN Control Register 1 */
#define EP_VCR1_VALUE_MASK WBGEN2_GEN_MASK(12, 1)
#define EP_VCR1_VALUE_SHIFT 12
#define EP_VCR1_VALUE_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define EP_VCR1_VALUE_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for register: Packet Filter Control Register 0 */
/* definitions for field: Microcode Memory Address in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_ADDR_MASK WBGEN2_GEN_MASK(0, 6)
#define EP_PFCR0_MM_ADDR_SHIFT 0
#define EP_PFCR0_MM_ADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define EP_PFCR0_MM_ADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Microcode Memory Write Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_WRITE_MASK WBGEN2_GEN_MASK(6, 1)
#define EP_PFCR0_MM_WRITE_SHIFT 6
#define EP_PFCR0_MM_WRITE_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define EP_PFCR0_MM_WRITE_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Packet Filter Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_ENABLE WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Microcode Memory Data (24 MSBs) in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_DATA_MSB_MASK WBGEN2_GEN_MASK(8, 24)
#define EP_PFCR0_MM_DATA_MSB_SHIFT 8
#define EP_PFCR0_MM_DATA_MSB_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define EP_PFCR0_MM_DATA_MSB_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Packet Filter Control Register 1 */
/* definitions for field: Microcode Memory Data (12 LSBs) in reg: Packet Filter Control Register 1 */
#define EP_PFCR1_MM_DATA_LSB_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_PFCR1_MM_DATA_LSB_SHIFT 0
#define EP_PFCR1_MM_DATA_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_PFCR1_MM_DATA_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for register: Traffic Class Assignment Register */
/* definitions for field: 802.1Q priority tag to Traffic Class map in reg: Traffic Class Assignment Register */
#define EP_TCAR_PCP_MAP_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_TCAR_PCP_MAP_SHIFT 0
#define EP_TCAR_PCP_MAP_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_TCAR_PCP_MAP_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: Flow Control Register */
......@@ -121,28 +200,6 @@
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
......@@ -160,16 +217,22 @@
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for register: MDIO Address/Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_ASR_RDATA_SHIFT 0
#define EP_MDIO_ASR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_ASR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO PHY Address in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_PHYAD_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_ASR_PHYAD_SHIFT 16
#define EP_MDIO_ASR_PHYAD_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_ASR_PHYAD_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for field: MDIO Ready in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
......@@ -180,6 +243,28 @@
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
......@@ -191,26 +276,36 @@ PACKED struct EP_WB {
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG Flow Control Register */
/* [0xc]: REG VLAN control register 0 */
uint32_t VCR0;
/* [0x10]: REG VLAN Control Register 1 */
uint32_t VCR1;
/* [0x14]: REG Packet Filter Control Register 0 */
uint32_t PFCR0;
/* [0x18]: REG Packet Filter Control Register 1 */
uint32_t PFCR1;
/* [0x1c]: REG Traffic Class Assignment Register */
uint32_t TCAR;
/* [0x20]: REG Flow Control Register */
uint32_t FCR;
/* [0x10]: REG Endpoint MAC address high part register */
/* [0x24]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x14]: REG Endpoint MAC address low part register */
/* [0x28]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x18]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x1c]: REG DMTD Status register */
uint32_t DMSR;
/* [0x20]: REG MDIO Control Register */
/* [0x2c]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x24]: REG MDIO Status Register */
uint32_t MDIO_SR;
/* [0x28]: REG Identification register */
/* [0x30]: REG MDIO Address/Status Register */
uint32_t MDIO_ASR;
/* [0x34]: REG Identification register */
uint32_t IDCODE;
/* [0x2c]: REG Debug/Status register */
/* [0x38]: REG Debug/Status register */
uint32_t DSR;
/* [0x3c]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x40]: REG DMTD Status register */
uint32_t DMSR;
/* padding to: 32 words */
uint32_t __padding_0[20];
uint32_t __padding_0[15];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
......
include/hw/minic_regs.h
+ 55
− 37
View file @ cfe1c9e7
/*
Register definitions for slave core: Mini NIC for WhiteRabbit
* File : ../../../software/include/hw/minic_regs.h
* File : minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Fri Aug 13 02:17:20 2010
* Created : Wed Nov 2 02:18:19 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -51,12 +51,43 @@
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
/* definitions for field: RX Accepted Packet Classes in reg: miNIC Control Register */
#define MINIC_MCR_RX_CLASS_MASK WBGEN2_GEN_MASK(16, 8)
#define MINIC_MCR_RX_CLASS_SHIFT 16
#define MINIC_MCR_RX_CLASS_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define MINIC_MCR_RX_CLASS_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for register: TX DMA Address */
/* definitions for register: RX DMA Address */
/* definitions for register: RX buffer size register */
/* definitions for register: TX timestamp register 0 */
/* definitions for field: Timestamp valid in reg: TX timestamp register 0 */
#define MINIC_TSR0_VALID WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Port ID in reg: TX timestamp register 0 */
#define MINIC_TSR0_PID_MASK WBGEN2_GEN_MASK(1, 5)
#define MINIC_TSR0_PID_SHIFT 1
#define MINIC_TSR0_PID_W(value) WBGEN2_GEN_WRITE(value, 1, 5)
#define MINIC_TSR0_PID_R(reg) WBGEN2_GEN_READ(reg, 1, 5)
/* definitions for field: Frame ID in reg: TX timestamp register 0 */
#define MINIC_TSR0_FID_MASK WBGEN2_GEN_MASK(6, 16)
#define MINIC_TSR0_FID_SHIFT 6
#define MINIC_TSR0_FID_W(value) WBGEN2_GEN_WRITE(value, 6, 16)
#define MINIC_TSR0_FID_R(reg) WBGEN2_GEN_READ(reg, 6, 16)
/* definitions for register: TX timestamp register 1 */
/* definitions for field: Timestamp value in reg: TX timestamp register 1 */
#define MINIC_TSR1_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSR1_TSVAL_SHIFT 0
#define MINIC_TSR1_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSR1_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Debug register */
/* definitions for field: interrupt counter in reg: Debug register */
......@@ -68,6 +99,20 @@
/* definitions for field: status of wb_irq_o line in reg: Debug register */
#define MINIC_DBGR_WB_IRQ_VAL WBGEN2_GEN_MASK(24, 1)
/* definitions for register: Memory protection reg */
/* definitions for field: address range lo in reg: Memory protection reg */
#define MINIC_MPROT_LO_MASK WBGEN2_GEN_MASK(0, 16)
#define MINIC_MPROT_LO_SHIFT 0
#define MINIC_MPROT_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MINIC_MPROT_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: address range hi in reg: Memory protection reg */
#define MINIC_MPROT_HI_MASK WBGEN2_GEN_MASK(16, 16)
#define MINIC_MPROT_HI_SHIFT 16
#define MINIC_MPROT_HI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define MINIC_MPROT_HI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Interrupt disable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
......@@ -111,33 +156,6 @@
/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */
/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT 0
#define MINIC_TSFIFO_R0_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */
/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT 0
#define MINIC_TSFIFO_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT 5
#define MINIC_TSFIFO_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 5, 16)
/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
......@@ -146,8 +164,14 @@
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x10]: REG Debug register */
#define MINIC_REG_DBGR 0x00000010
/* [0x10]: REG TX timestamp register 0 */
#define MINIC_REG_TSR0 0x00000010
/* [0x14]: REG TX timestamp register 1 */
#define MINIC_REG_TSR1 0x00000014
/* [0x18]: REG Debug register */
#define MINIC_REG_DBGR 0x00000018
/* [0x1c]: REG Memory protection reg */
#define MINIC_REG_MPROT 0x0000001c
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
......@@ -156,10 +180,4 @@
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038
#endif
include/hw/pps_gen_regs.h
+ 21
− 6
View file @ cfe1c9e7
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ../../../software/include/hw/pps_gen_regs.h
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Sat Sep 11 22:22:55 2010
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Sun Oct 30 01:54:53 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -60,6 +62,17 @@
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
......@@ -74,4 +87,6 @@
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
#endif
include/hw/softpll_regs.h
+ 24
− 10
View file @ cfe1c9e7
......@@ -3,7 +3,7 @@
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from wr_softpll.wb
* Created : Sat Apr 9 13:29:44 2011
* Created : Thu Oct 27 23:54:06 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
......@@ -45,16 +45,26 @@
#define SPLL_CSR_TAG_RDY_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define SPLL_CSR_TAG_RDY_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: Aux clock locking enable in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Aux clock locked flag (to slave) in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_LOCK WBGEN2_GEN_MASK(9, 1)
/* definitions for register: HPLL Frequency Error */
/* definitions for register: DMPLL Tag ref */
/* definitions for register: DMPLL Tag fb */
/* definitions for register: DMPLL Tag aux */
/* definitions for register: HPLL DAC Output */
/* definitions for register: DMPLL DAC Output */
/* definitions for register: AUX DAC Output */
/* definitions for register: Deglitcher threshold */
/* definitions for register: Interrupt disable register */
......@@ -86,21 +96,25 @@ PACKED struct SPLL_WB {
uint32_t TAG_REF;
/* [0xc]: REG DMPLL Tag fb */
uint32_t TAG_FB;
/* [0x10]: REG HPLL DAC Output */
/* [0x10]: REG DMPLL Tag aux */
uint32_t TAG_AUX;
/* [0x14]: REG HPLL DAC Output */
uint32_t DAC_HPLL;
/* [0x14]: REG DMPLL DAC Output */
/* [0x18]: REG DMPLL DAC Output */
uint32_t DAC_DMPLL;
/* [0x18]: REG Deglitcher threshold */
/* [0x1c]: REG AUX DAC Output */
uint32_t DAC_AUX;
/* [0x20]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* padding to: 8 words */
uint32_t __padding_0[1];
/* [0x20]: REG Interrupt disable register */
/* padding to: 16 words */
uint32_t __padding_0[7];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x24]: REG Interrupt enable register */
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x28]: REG Interrupt mask register */
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x2c]: REG Interrupt status register */
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
};
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment