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Commit 8db4cfd9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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devices updated

parent dfbcc8a2
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dev/endpoint.c
+ 58
− 13
View file @ 8db4cfd9
#include <stdio.h>
#include "board.h"
#include<endpoint.h>
#include <hw/endpoint_regs.h>
#include <hw/endpoint_mdio.h>
#define DMTD_AVG_SAMPLES 256
#define DMTD_MAX_PHASE 16384
#define UIS_PER_SERIAL_BIT 800
static int autoneg_enabled;
......@@ -34,14 +32,24 @@ static void pcs_write(int location,
}
static void set_mac_addr(uint8_t dev_addr[])
{
EP->MACL = ((uint32_t)dev_addr[3] << 24)
| ((uint32_t)dev_addr[2] << 16)
| ((uint32_t)dev_addr[1] << 8)
| ((uint32_t)dev_addr[0]);
{
EP->MACL = ((uint32_t)dev_addr[2] << 24)
| ((uint32_t)dev_addr[3] << 16)
| ((uint32_t)dev_addr[4] << 8)
| ((uint32_t)dev_addr[5]);
EP->MACH = ((uint32_t)dev_addr[0] << 8)
| ((uint32_t)dev_addr[1]);
}
EP->MACH = ((uint32_t)dev_addr[5] << 8)
| ((uint32_t)dev_addr[4]);
void get_mac_addr(uint8_t dev_addr[])
{
dev_addr[5] = (uint8_t)(EP->MACL & 0x000000ff);
dev_addr[4] = (uint8_t)(EP->MACL & 0x0000ff00) >> 8;
dev_addr[3] = (uint8_t)(EP->MACL & 0x00ff0000) >> 16;
dev_addr[2] = (uint8_t)(EP->MACL & 0xff000000) >> 24;
dev_addr[1] = (uint8_t)(EP->MACH & 0x000000ff);
dev_addr[0] = (uint8_t)(EP->MACH & 0x0000ff00) >> 8;
}
......@@ -71,8 +79,13 @@ int ep_enable(int enabled, int autoneg)
EP->ECR = EP_ECR_TX_EN_FRA | EP_ECR_RX_EN_FRA | EP_ECR_RST_CNT;
autoneg_enabled = autoneg;
pcs_write(MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
#if 1
pcs_write(MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
timer_delay(2000);
pcs_write(MDIO_REG_MCR, 0); /* reset the PHY */
// pcs_write(MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
#endif
pcs_write(MDIO_REG_ADVERTISE, 0);
mcr = MDIO_MCR_SPEED1000_MASK | MDIO_MCR_FULLDPLX_MASK;
......@@ -98,6 +111,7 @@ int ep_link_up()
return (msr & flags) == flags ? 1 : 0;
}
int ep_get_deltas(uint32_t *delta_tx, uint32_t *delta_rx)
{
*delta_tx = 0;
......@@ -108,5 +122,36 @@ void ep_show_counters()
{
int i;
for(i=0;i<16;i++)
mprintf("cntr%d = %d\n", i, EP->RMON_RAM[i]);
TRACE_DEV("cntr%d = %d\n", i, EP->RMON_RAM[i]);
}
int ep_get_psval(int32_t *psval)
{
uint32_t val;
val = EP->DMSR;
if(val & EP_DMSR_PS_RDY)
*psval = EP_DMSR_PS_VAL_R(val);
else
*psval = 0;
return val & EP_DMSR_PS_RDY;
}
int ep_cal_pattern_enable()
{
uint32_t val;
val = pcs_read(MDIO_REG_WR_SPEC);
val |= MDIO_WR_SPEC_TX_CAL;
pcs_write(MDIO_REG_WR_SPEC, val);
return 0;
}
int ep_cal_pattern_disable()
{
uint32_t val;
val = pcs_read(MDIO_REG_WR_SPEC);
val &= (~MDIO_WR_SPEC_TX_CAL);
pcs_write(MDIO_REG_WR_SPEC, val);
}
dev/minic.c
+ 48
− 9
View file @ 8db4cfd9
......@@ -37,8 +37,8 @@
fc = (raw >> 28) & 0xf;
static volatile uint32_t dma_tx_buf[MINIC_DMA_RX_BUF_SIZE / 4];
static volatile uint32_t dma_rx_buf[MINIC_DMA_TX_BUF_SIZE / 4];
static volatile uint32_t dma_tx_buf[MINIC_DMA_TX_BUF_SIZE / 4];
static volatile uint32_t dma_rx_buf[MINIC_DMA_RX_BUF_SIZE / 4];
struct wr_minic {
volatile uint32_t *rx_head, *rx_base;
......@@ -72,6 +72,7 @@ static void minic_new_rx_buffer()
minic_writel(MINIC_REG_MCR, 0);
minic_writel(MINIC_REG_RX_ADDR, (uint32_t) minic.rx_base);
minic_writel(MINIC_REG_RX_AVAIL, (minic.rx_size - MINIC_MTU) >> 2);
// TRACE_DEV("Sizeof: %d Size : %d Avail: %d\n", minic.rx_size, (minic.rx_size - MINIC_MTU) >> 2);
minic_writel(MINIC_REG_MCR, MINIC_MCR_RX_EN);
}
......@@ -87,7 +88,10 @@ static void minic_new_tx_buffer()
void minic_init()
{
minic_writel(MINIC_REG_EIC_IDR, MINIC_EIC_IDR_RX);
minic_writel(MINIC_REG_EIC_ISR, MINIC_EIC_ISR_RX);
minic.rx_base = dma_rx_buf;
minic.rx_size = sizeof(dma_rx_buf);
......@@ -99,13 +103,18 @@ void minic_init()
minic_writel(MINIC_REG_EIC_IER, MINIC_EIC_IER_RX);
}
void minic_disable()
{
minic_writel(MINIC_REG_MCR, 0);
}
int minic_poll_rx()
{
uint32_t isr;
isr = minic_readl(MINIC_REG_EIC_ISR);
return isr;
return (isr & MINIC_EIC_ISR_RX) ? 1 : 0;//>>1;
}
int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_timestamp *hwts)
......@@ -121,10 +130,12 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
return 0;
desc_hdr = *minic.rx_head;
// TRACE_DEV("RX_FRAME_ENTER\n\nRxHead %x buffer at %x\n", minic.rx_head, minic.rx_base);
if(!RX_DESC_VALID(desc_hdr)) /* invalid descriptor? Weird, the RX_ADDR seems to be saying something different. Ignore the packet and purge the RX buffer. */
{
// mprintf("weird, invalid RX descriptor (%x, head %x)\n", desc_hdr, rx_head);
TRACE_DEV("weird, invalid RX descriptor (%x, head %x)\n", desc_hdr, minic.rx_head);
minic_new_rx_buffer();
return 0;
}
......@@ -132,6 +143,8 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
payload_size = RX_DESC_SIZE(desc_hdr);
num_words = ((payload_size + 3) >> 2) + 1;
// TRACE_DEV("NWords %d\n", num_words);
/* valid packet */
if(!RX_DESC_ERROR(desc_hdr))
{
......@@ -161,7 +174,11 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
else
hwts->ahead = 0;
hwts->nsec = counter_r * 8;
TRACE_DEV("TS minic_rx_frame: %d.%d\n", hwts->utc, hwts->nsec);
}
n_recvd = (buf_size < payload_size ? buf_size : payload_size);
......@@ -169,14 +186,23 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
/* FIXME: VLAN support */
memcpy(hdr, (void*)minic.rx_head + 4, ETH_HEADER_SIZE);
//TRACE_DEV("%s: packet: ", __FUNCTION__);
//for(i=0; i<ETH_HEADER_SIZE; i++) TRACE_DEV("%x ", *(hdr+i));
memcpy(payload, (void*)minic.rx_head + 4 + ETH_HEADER_SIZE, n_recvd - ETH_HEADER_SIZE);
//for(i=0; i<n_recvd-ETH_HEADER_SIZE; i++) TRACE_DEV("%x ", *(payload+i));
/* for(i=0;i<n_recvd;i++)
mprintf("%x ", buf[i]);
mprintf("---\n");*/
/* for(i=0;i<n_recvd-14;i++)
TRACE_DEV("%x ", payload[i]);
TRACE_DEV("---\n");
*/
// TRACE_DEV("nwords_avant: %d\n", num_words);
minic.rx_head += num_words;
} else { // RX_DESC_ERROR
// TRACE_DEV("nwords_avant_err: %d\n", num_words);
minic.rx_head += num_words;
}
......@@ -184,6 +210,7 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
if(rx_addr_cur < (uint32_t)minic.rx_head) /* nothing new in the buffer? */
{
// TRACE_DEV("MoreData? %x, head %x\n", rx_addr_cur, minic.rx_head);
if(minic_readl(MINIC_REG_MCR) & MINIC_MCR_RX_FULL)
minic_new_rx_buffer();
......@@ -201,12 +228,21 @@ int minic_tx_frame(uint8_t *hdr, uint8_t *payload, uint32_t size, struct hw_time
{
uint32_t d_hdr, mcr, nwords;
minic_new_tx_buffer();
nwords = ((size + 1) >> 1) - 1;
memset(minic.tx_head, 0x0, size + 16);
memset((void*)minic.tx_head + 4, 0, size < 60 ? 60 : size);
memcpy((void*)minic.tx_head + 4, hdr, ETH_HEADER_SIZE);
memcpy((void*)minic.tx_head + 4 + ETH_HEADER_SIZE, payload, size - ETH_HEADER_SIZE);
if(size < 60)
size = 60;
nwords = ((size + 1) >> 1) - 1;
if(hwts)
{
......@@ -249,6 +285,9 @@ int minic_tx_frame(uint8_t *hdr, uint8_t *payload, uint32_t size, struct hw_time
hwts->utc = utc;
hwts->ahead = 0;
hwts->nsec = counter_r * 8;
TRACE_DEV("TS minic_tx_frame: %d.%d\n", hwts->utc, hwts->nsec);
}
tx_oob_val++;
......
dev/pps_gen.c
+ 10
− 4
View file @ 8db4cfd9
......@@ -24,7 +24,7 @@ void pps_gen_init()
ppsg_writel( PPSG_REG_CR, cr);
ppsg_writel( PPSG_REG_ADJ_UTCLO, 1285700840);
ppsg_writel( PPSG_REG_ADJ_UTCLO, 100 );
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, 0);
......@@ -36,24 +36,30 @@ void pps_gen_adjust_nsec(int32_t how_much)
{
uint32_t cr;
mprintf("AdjustPPS: %d nanoseconds\n", how_much);
TRACE_DEV("ADJ: nsec %d nanoseconds\n", how_much);
#if 1
ppsg_writel( PPSG_REG_ADJ_UTCLO, 0);
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, ( how_much / 8 ));
ppsg_writel( PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ);
#endif
}
void shw_pps_gen_adjust_utc(int32_t how_much)
void pps_gen_adjust_utc(int32_t how_much)
{
uint32_t cr;
mprintf("AdjustUTC: %d seconds\n", how_much);
#if 1
TRACE_DEV("ADJ: utc %d seconds\n", how_much);
ppsg_writel( PPSG_REG_ADJ_UTCLO, how_much);
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, 0);
ppsg_writel( PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ);
#endif
}
int pps_gen_busy()
......
dev/softpll.c
+ 18
− 5
View file @ 8db4cfd9
......@@ -77,7 +77,7 @@ const struct softpll_config pll_cfg =
10, // p_ki
1000, // lock detect samples
300, // lock detect threshold
500, // lock detect threshold
500, // delock threshold
32000, // DPLL dac bias
1000 // deglitcher threshold
......@@ -263,10 +263,12 @@ void _irq_entry()
tag_ref = pstate.d_tag_ref_d0 ;
tag_fb += pstate.d_p_setpoint;
tag_fb += pstate.d_p_setpoint; // was tag_fb
if(tag_fb > (1<<TAG_BITS)) tag_fb -= (1<<TAG_BITS);
if(tag_fb < 0) tag_fb += (1<<TAG_BITS);
tag_fb &= (1<<TAG_BITS)-1;
//if(tag_ref > (1<<TAG_BITS)) tag_ref -= (1<<TAG_BITS);
//if(tag_ref < 0) tag_ref += (1<<TAG_BITS);
if(tag_fb_ready)
{
......@@ -321,6 +323,10 @@ void softpll_enable()
int softpll_check_lock()
{
TRACE_DEV("LCK h:f%d l%d d: f%d l%d\n",
pstate.h_freq_mode ,pstate.h_locked,
pstate.d_freq_mode, pstate.d_locked);
return pstate.h_locked && pstate.d_locked;
}
......@@ -331,7 +337,9 @@ int softpll_busy()
void softpll_set_phase(int ps)
{
pstate.d_phase_shift = ps;
pstate.d_phase_shift = (int32_t) (((int64_t)ps * 16384LL) / 8000LL);
TRACE_DEV("ADJ: phase %d [ps], %d units\n", ps, pstate.d_phase_shift);
}
void softpll_disable()
......@@ -339,3 +347,8 @@ void softpll_disable()
SPLL->CSR = 0;
disable_irq();
}
int softpll_get_setpoint()
{
return pstate.d_p_setpoint;
}
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