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wr2rf-vme
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wr2rf-vme
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RF signal, distributed to trigger unit flip flops looks awful
#74
· opened
Jan 22, 2021
by
John Gill
Layout V2
critical
hw
CLOSED
2
updated
Feb 05, 2021
Unconnected 5V power rail
#69
· opened
Dec 14, 2020
by
John Gill
Layout V2
critical
hw
CLOSED
1
updated
Feb 05, 2021
trigger regulators
#48
· opened
Oct 16, 2020
by
Mattia Rizzi
layout
critical
CLOSED
1
updated
Oct 19, 2020
P1V0 plane
#47
· opened
Oct 16, 2020
by
Mattia Rizzi
layout
critical
CLOSED
1
updated
Oct 19, 2020
Replace ADCLK925 with LTC6957-2
#44
· opened
Jun 29, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
18
updated
Jul 08, 2020
Missing correct symbols in rf_main sheet
#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
DAC clock - AC coupling
#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
pulse shaper - vcc connected to vin
#20
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
critical
hw
CLOSED
1
updated
May 12, 2020
Replace capacitors and inductors with proper symbols in RF main sheet
#9
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
4
updated
Jun 18, 2020
Verify that the BE-RF VME crate power supplies can deliver enough current on P1
#4
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
26
updated
Jul 07, 2020
IRLML2803PBF must be replaced with PMV40UN2R
#2
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
2
updated
Feb 05, 2021
Front panel cannot be fitted
#80
· opened
Jan 29, 2021
by
John Gill
Layout V2
for-DEM
important
CLOSED
2
updated
Feb 15, 2021
Front-panel design and fabrication
#79
· opened
Jan 29, 2021
by
Erik van der Bij
Layout V2
for-DEM
important
CLOSED
1
updated
Jul 06, 2021
OCXO sense goes to FPGA digital input
#71
· opened
Dec 14, 2020
by
Dimitris Lampridis
Layout V2
hw
important
CLOSED
1
updated
Feb 05, 2021
More GND stitching vias around criticial signal vias
#66
· opened
Oct 23, 2020
by
Tomasz Wlostowski
layout
for-DEM
important
CLOSED
1
updated
Oct 27, 2020
SI/PI: check IR drop for the core FPGA power rail PDN
#52
· opened
Oct 19, 2020
by
Tomasz Wlostowski
important
CLOSED
1
updated
Oct 19, 2020
Fix M12V connections around IC86
#49
· opened
Oct 19, 2020
by
Tomasz Wlostowski
important
CLOSED
1
updated
Oct 19, 2020
Delay matching of RF_CH2.MAIN.IQDAC data lines
#46
· opened
Oct 15, 2020
by
Mattia Rizzi
layout
for-DEM
important
CLOSED
3
updated
Oct 23, 2020
Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
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