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wr2rf-vme
Issues
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5
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92
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DOC: Delay Compensation
#92
· opened
Sep 09, 2023
by
Gregoire Hagmann
1
updated
Oct 10, 2023
ocxo current sense saturate
#91
· opened
May 09, 2023
by
Tristan Gingold
0
updated
May 09, 2023
10 MHz output is subject to metastability problems and cannot be aligned with PPS
#90
· opened
Feb 21, 2022
by
John Gill
0
updated
Dec 12, 2022
VME slot and address space
#89
· opened
Jun 21, 2021
by
Tristan Gingold
CLOSED
1
updated
Sep 16, 2021
V2: Front-panel ELMA reference numbers wrong
#88
· opened
Mar 08, 2021
by
Erik van der Bij
0
updated
Mar 08, 2021
Clock level at input of the IQ DACs too low.
#87
· opened
Mar 08, 2021
by
Tomasz Wlostowski
Layout V2
0
updated
Mar 08, 2021
V2: change EP195 delay line to SY89295UMG
#86
· opened
Feb 11, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
2
updated
Feb 15, 2021
EXT REF I/O: PPS / 10M mux direction line needs opposite polarity
#85
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
minor
CLOSED
1
updated
Feb 05, 2021
Change electrolytic caps to more reliable series
#84
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
Front panel: J9 very close to the front panel handle
#83
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
Board 0002 cannot observe output from IC34 to OUT_RAW_3_P
#82
· opened
Feb 02, 2021
by
John Gill
CLOSED
1
updated
Feb 21, 2022
Front panel middle fastening not aligned with PCB
#81
· opened
Jan 29, 2021
by
John Gill
Layout V2
for-DEM
CLOSED
4
updated
Feb 12, 2021
Front panel cannot be fitted
#80
· opened
Jan 29, 2021
by
John Gill
Layout V2
for-DEM
important
CLOSED
2
updated
Feb 15, 2021
Front-panel design and fabrication
#79
· opened
Jan 29, 2021
by
Erik van der Bij
Layout V2
for-DEM
important
CLOSED
1
updated
Jul 06, 2021
Ground plane not connected
#78
· opened
Jan 28, 2021
by
John Gill
CLOSED
2
updated
Feb 15, 2021
Board #0001 fails to configure the LTC6950 PLL
#77
· opened
Jan 26, 2021
by
John Gill
CLOSED
1
updated
Feb 25, 2021
The PCB labelling of the SFP connectors is inconsistent with front panel labelling
#76
· opened
Jan 22, 2021
by
John Gill
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
IQ DAC timing
#75
· opened
Jan 22, 2021
by
John Gill
CLOSED
1
updated
Feb 26, 2021
RF signal, distributed to trigger unit flip flops looks awful
#74
· opened
Jan 22, 2021
by
John Gill
Layout V2
critical
hw
CLOSED
2
updated
Feb 05, 2021
Board 0001 doesn't configure a working FPGA
#73
· opened
Jan 18, 2021
by
John Gill
CLOSED
3
updated
Feb 05, 2021
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