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wr2rf-vme
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wr2rf-vme
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Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
Power sequencing and consumption
#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
Dielectric of ceramic capacitors in the RF path
#34
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
CLOSED
3
updated
Jun 10, 2020
DC coupling for FPGA clock ECL to LVDS
#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
Trigger unit output glitches
#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
FPGA configuration IO
#28
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
xdc update
CLOSED
2
updated
Jun 29, 2020
Front panel Timing I/O
#25
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
2
updated
Jun 24, 2020
Faster buffers for front panel I/O
#17
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
important
xdc update
CLOSED
7
updated
Jun 29, 2020
Optimise BOM
#12
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
5
updated
Jul 15, 2020
RF amplifier checked?
#10
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Apr 27, 2020
Check terminations on shared SPI lines
#8
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Jun 09, 2020
Change licence to CERN-OHL-S v2
#1
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Feb 05, 2021