Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
wr2rf-vme
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
wr2rf-vme
Issues
Open
0
Closed
26
All
26
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
Missing correct symbols in rf_main sheet
#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
BOM de de-optimization
#38
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
CLOSED
1
updated
Jun 06, 2020
Power sequencing and consumption
#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
Main RF generation
#33
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
3
updated
Jun 09, 2020
DC coupling for FPGA clock ECL to LVDS
#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
Trigger unit output glitches
#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
wire length matching
#29
· opened
May 13, 2020
by
Tristan Gingold
Schematic done
hw
minor
CLOSED
4
updated
Jun 17, 2020
FPGA configuration IO
#28
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
xdc update
CLOSED
2
updated
Jun 29, 2020
1V0 LDO current sharing scheme - questions
#26
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
question
CLOSED
8
updated
Jun 16, 2020
Front panel Timing I/O
#25
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
2
updated
Jun 24, 2020
Faster buffers for front panel I/O
#17
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
important
xdc update
CLOSED
7
updated
Jun 29, 2020
Address switch
#16
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
minor
xdc update
CLOSED
4
updated
Jun 29, 2020
Name change for NETs: CLK_FPGA_62M5_p and CLK_FPGA_62M5_p
#14
· opened
May 06, 2020
by
John Gill
Schematic done
hdl
hw
minor
CLOSED
3
updated
Jun 08, 2020
Optimise BOM
#12
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
5
updated
Jul 15, 2020
Are we ok with 128Mbit flash?
#11
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
question
CLOSED
3
updated
Apr 27, 2020
RF amplifier checked?
#10
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Apr 27, 2020
Check terminations on shared SPI lines
#8
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Jun 09, 2020
Series resistors and buffers on VME P0 TTL lines
#7
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
minor
xdc update
CLOSED
8
updated
Jun 29, 2020
Prev
1
2
Next