Fix FPGA pin assignment
Some pins in the timing I/O banks have incorrect placement (clock routing):
NOW WAS NAME
E11 H14 TMG_CLK_IN1
C12 A15 TMG_CLK_IN2
H14 C11 TMG_IO_IN3
A15 C12 TMG_IO_IN4
C14 E11 SFP2_TX_DISABLEs
Some pins in the timing I/O banks have incorrect placement (clock routing):
NOW WAS NAME
E11 H14 TMG_CLK_IN1
C12 A15 TMG_CLK_IN2
H14 C11 TMG_IO_IN3
A15 C12 TMG_IO_IN4
C14 E11 SFP2_TX_DISABLEs