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12
- trigger regulators
- P1V0 plane
- More GND stitching vias around criticial signal vias
- Delay matching of RF_CH2.MAIN.IQDAC data lines
- Increase distance between J1 and SFP
- Remove soldermask from ESD strip
- With just one pair of vias, connect the fast caps first, not the big ones
- Consider adding ground guard traces to the OCXO clock and the GTX lines
- Plane resonance at low frequencies (around 300MHz)
- Net NetC304_2 (for IC86's feedback) passes right over LVDS signals
- Fix FPGA pin assignment
- DRC rules incomplete for vias under pads.