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wr2rf-vme
Commits
f3a54cc5
Commit
f3a54cc5
authored
Jun 05, 2023
by
Tristan Gingold
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11 additions
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11 deletions
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-11
wr2rf_vme.tcl
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
+5
-3
wr2rf_vme.xdc
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
+6
-8
No files found.
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
View file @
f3a54cc5
...
@@ -26,6 +26,8 @@ if {$swap_sfp eq "true"} {
...
@@ -26,6 +26,8 @@ if {$swap_sfp eq "true"} {
read_xdc
$proj
Dir/$
{
top
}
_sfp.xdc
read_xdc
$proj
Dir/$
{
top
}
_sfp.xdc
}
}
read_xdc
$proj
Dir/$
{
top
}
.xdc
read_xdc
$proj
Dir/$
{
top
}
.xdc
read_xdc
$proj
Dir/wrcore.xdc
read_xdc
$proj
Dir/gencores_constraints.xdc
set
start_time
[
clock
seconds
]
set
start_time
[
clock
seconds
]
...
@@ -33,9 +35,9 @@ set start_time [clock seconds]
...
@@ -33,9 +35,9 @@ set start_time [clock seconds]
synth_design -top
${top}
-part
${device}
>
${top}
_synth.log
synth_design -top
${top}
-part
${device}
>
${top}
_synth.log
write_checkpoint -force
${top}
_synth
write_checkpoint -force
${top}
_synth
source
wr2rf_async_regs.tcl
#
source wr2rf_async_regs.tcl
source
wr2rf_maxdelays.tcl
#
source wr2rf_maxdelays.tcl
source
wr2rf_dmtd_falsepath.tcl
#
source wr2rf_dmtd_falsepath.tcl
source
wr2rf_t1sync_falsepath.tcl
source
wr2rf_t1sync_falsepath.tcl
#opt_design -directive Explore -verbose > ${top
}
_opt.log
#opt_design -directive Explore -verbose > ${top
}
_opt.log
...
...
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @
f3a54cc5
...
@@ -254,8 +254,6 @@ set_property OFFCHIP_TERM NONE [get_ports wr_dac_ocxo_din_o]
...
@@ -254,8 +254,6 @@ set_property OFFCHIP_TERM NONE [get_ports wr_dac_ocxo_din_o]
set_property OFFCHIP_TERM NONE [get_ports wr_dac_ocxo_sclk_o]
set_property OFFCHIP_TERM NONE [get_ports wr_dac_ocxo_sclk_o]
set_property OFFCHIP_TERM NONE [get_ports wr_eeprom1_scl_b]
set_property OFFCHIP_TERM NONE [get_ports wr_eeprom1_scl_b]
set_property OFFCHIP_TERM NONE [get_ports wr_eeprom2_scl_b]
set_property OFFCHIP_TERM NONE [get_ports wr_eeprom2_scl_b]
set_property OFFCHIP_TERM NONE [get_ports ocxo_sense_p_i]
set_property OFFCHIP_TERM NONE [get_ports ocxo_sense_n_i]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[0]}]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[0]}]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[1]}]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[1]}]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[2]}]
set_property IOSTANDARD LVDS [get_ports {rf1_iqdac_data_p_o[2]}]
...
@@ -1072,10 +1070,10 @@ create_clock -period 4.444 -name clk_rf2_t1 -waveform {0.000 2.222} [get_
...
@@ -1072,10 +1070,10 @@ create_clock -period 4.444 -name clk_rf2_t1 -waveform {0.000 2.222} [get_
create_clock -period 4.444 -name clk_rf2_t2 -waveform {0.000 2.222} [get_ports {rf2_t2_clk_p_i}]
create_clock -period 4.444 -name clk_rf2_t2 -waveform {0.000 2.222} [get_ports {rf2_t2_clk_p_i}]
# Transceivers need a create_clock - cannot propagate from clk_125m_gtx_p_i
# Transceivers need a create_clock - cannot propagate from clk_125m_gtx_p_i
create_clock -period
16.000 [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLK
]
create_clock -period
4.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRIC
]
create_clock -period
16.000 [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLKFABRIC
]
create_clock -period
4.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK
]
create_
clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRIC
]
create_
generated_clock -name gtx_txoutclk -divide_by 1 -add -source [get_ports -filter { NAME =~ "*clk_sys_62m5_p_i*" && DIRECTION == "IN" }] -master_clock clk_sys [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLK
]
create_
clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK
]
create_
generated_clock -name gtx_txoutclkfabric -divide_by 1 -add -source [get_ports -filter { NAME =~ "*clk_sys_62m5_p_i*" && DIRECTION == "IN" }] -master_clock clk_sys [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLKFABRIC
]
# Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
# Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
create_generated_clock -name clk_sys_bgmux -divide_by 1 -add -master_clock clk_sys -source [get_ports {clk_sys_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
create_generated_clock -name clk_sys_bgmux -divide_by 1 -add -master_clock clk_sys -source [get_ports {clk_sys_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
...
@@ -1117,8 +1115,8 @@ set_clock_groups -name async_vtu1_sys -asynchronous -group {clk_vtu} -gr
...
@@ -1117,8 +1115,8 @@ set_clock_groups -name async_vtu1_sys -asynchronous -group {clk_vtu} -gr
set_clock_groups -name async_vtu2_sys -asynchronous -group {clk_vtu_1} -group {clk_sys_bgmux}
set_clock_groups -name async_vtu2_sys -asynchronous -group {clk_vtu_1} -group {clk_sys_bgmux}
set_clock_groups -name async_dmtd_clkout2 -asynchronous -group {clk_dmtd_bgmux} -group {clkout2}
set_clock_groups -name async_dmtd_clkout2 -asynchronous -group {clk_dmtd_bgmux} -group {clkout2}
set_clock_groups -name async_dmtd_clkout5 -asynchronous -group {clk_dmtd_bgmux} -group {clkout5}
#
set_clock_groups -name async_dmtd_clkout5 -asynchronous -group {clk_dmtd_bgmux} -group {clkout5}
set_clock_groups -name async_clkout5_dmtd -asynchronous -group {clkout5} -group {clk_dmtd_bgmux}
#
set_clock_groups -name async_clkout5_dmtd -asynchronous -group {clkout5} -group {clk_dmtd_bgmux}
###################################
###################################
# Cleanly resample nco_reset in the RF clock domain - use a little less time than the wr cycle time
# Cleanly resample nco_reset in the RF clock domain - use a little less time than the wr cycle time
...
...
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