wr2rf_vme: adjust transceiver

d15685f0 · Tristan Gingold · 4e0b16fd · d15685f0
Commit d15685f0 authored Jun 05, 2023 by Tristan Gingold
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Showing with 2 additions and 18 deletions

wr2rf_vme.vhd hdl/top/wr2rf_vme/wr2rf_vme.vhd +2 -18

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--- a/hdl/top/wr2rf_vme/wr2rf_vme.vhd
+++ b/hdl/top/wr2rf_vme/wr2rf_vme.vhd
@@ -370,9 +370,6 @@ architecture rtl of wr2rf_vme is
  signal clk_ext_rst        : std_logic;


-  signal gtx_qpll_ref_clk, gtx_qpll_clk, gtx_qpll_locked : std_logic;
-  signal gtx_qpll_reset                                  : std_logic;
-
  --loopen_i determines (7 Series Transceiver User Guide(UG476) Figure 2-23 and Table 2-37):
  --'0' => gtx_loopback = "000" => normal operation
  --'1' => gtx_loopback = "100" => Far-end PMA Loopback
@@ -827,17 +824,6 @@ begin
          clk_ext_locked_o  => clk_ext_mul_locked,
          clk_ext_125m_o    => clk_ext_mul );

-    inst_GTX_QPLL : entity work.wr_gtx_phy_kintex7_lp_qpll
-        generic map (
-            g_simulation => g_simulation )
-        port map (
-            rst_i          => gtx_qpll_reset,
-            clk_gtx_i      => clk_gtx_125m,
-            clk_sys_i      => clk_sys_62m5,
-            locked_o       => gtx_qpll_locked,
-            qpll_clk_o     => gtx_qpll_clk,
-            qpll_ref_clk_o => gtx_qpll_ref_clk );
-
    phy16_in.ref_clk        <= clk_sys_62m5;
    phy16_in.sfp_tx_fault   <= sfp1_tx_fault_i;
    phy16_in.sfp_los        <= sfp1_los_i;
@@ -849,10 +835,7 @@ begin
      port map(
            clk_sys_i => clk_sys_62m5,
            rst_sys_n_i => wrcore_reset_n,
-            qpll_clk_i         => gtx_qpll_clk,
-            qpll_ref_clk_i     => gtx_qpll_ref_clk,
-            qpll_locked_i      => gtx_qpll_locked,
-            qpll_reset_o       => gtx_qpll_reset,
+            clk_gtx_i          => clk_gtx_125m,
            clk_dmtd_i         => clk_dmtd_62m5,
            clk_ref_i          => clk_sys_62m5,
            tx_clk_o           => open,
@@ -875,6 +858,7 @@ begin
            pad_txp_o          => sfp1_tx_p_o,
            pad_rxn_i          => sfp1_rx_n_i,
            pad_rxp_i          => sfp1_rx_p_i,
+            fmon_clk_o         => open,
            mdio_slave_i       => phy_mdio_out,
            mdio_slave_o       => phy_mdio_in);