Skip to content

W
wr2rf-vme
Commit d82f7502 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

wr2rf: adjust registers map and signals for io changes.

parent 9d687efc
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 223 additions and 227 deletions
hdl/rtl/trigunit_regs.vhd
View file @ d82f7502
This diff is collapsed.
hdl/rtl/wr2rf_core.vhd
View file @ d82f7502
......@@ -58,9 +58,9 @@ entity wr2rf_core is
tmg_clk_term_en_o : out std_logic_vector(2 downto 1);
tmg_io_term_en_o : out std_logic_vector(4 downto 1);
tmg_clk_oe_o : out std_logic_vector(1 downto 0);
tmg_io_dir_o : out std_logic;
ext_ref_dir_o : out std_logic;
tmg_clk_oe_o : out std_logic_vector(1 downto 0);
tmg_io_oe_o : out std_logic_vector(4 downto 1);
ext_ref_dir_o : out std_logic;
dds_cs_n_o : out std_logic;
rf1_iqdac_cs_n_o : out std_logic;
......@@ -143,8 +143,8 @@ begin
init_tmg_io_term_o => tmg_io_term_en_o,
init_tmg_clk_term_o => tmg_clk_term_en_o,
init_tmg_clk_oe_o => tmg_clk_oe_o,
init_tmg_io_dir_o => tmg_io_dir_o,
init_tmg_clk_oe_o => tmg_clk_oe_o,
init_tmg_io_oe_o => tmg_io_oe_o,
init_pin_ctrl_ext_ref_dir_o => ext_ref_dir_o,
init_pll_spi_i => pll_spi_in,
......
hdl/rtl/wr2rf_init_regs.cheby
View file @ d82f7502
......@@ -55,18 +55,18 @@ memory-map:
name: io_term
description: terminations for UBT
range: 3-0
- field:
name: io_oe
description: Output enable for general IO signals (not clocks)
range: 7-4
- field:
name: clk_term
description: terminations for UBT
range: 5-4
range: 9-8
- field:
name: clk_oe
description: independent bidirectional control for clock outputs
range: 9-8
- field:
name: io_dir
description: bidirectional control for x4 general IO signals (not clocks)
range: 10
range: 11-10
- reg:
name: pin_ctrl
description: timing io grouping of signals
......
hdl/rtl/wr2rf_init_rf_regs.vhd
View file @ d82f7502
-- Do not edit. Generated on Wed May 20 15:05:47 2020 by tgingold
-- Do not edit. Generated on Mon Jun 29 17:15:38 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......@@ -355,43 +355,43 @@ begin
rf2_ch_1_csr_wreq <= '0';
rf2_ch_1_delay_wreq <= '0';
case wr_adr_d0(4 downto 1) is
when "0000" =>
when "0000" =>
-- Reg rf1_common
rf1_common_wreq <= wr_req_d0;
wr_ack_int <= rf1_common_wack;
when "0100" =>
when "0100" =>
-- Reg rf1_ch_0_csr
rf1_ch_0_csr_wreq <= wr_req_d0;
wr_ack_int <= rf1_ch_0_csr_wack;
when "0101" =>
when "0101" =>
-- Reg rf1_ch_0_delay
rf1_ch_0_delay_wreq <= wr_req_d0;
wr_ack_int <= rf1_ch_0_delay_wack;
when "0110" =>
when "0110" =>
-- Reg rf1_ch_1_csr
rf1_ch_1_csr_wreq <= wr_req_d0;
wr_ack_int <= rf1_ch_1_csr_wack;
when "0111" =>
when "0111" =>
-- Reg rf1_ch_1_delay
rf1_ch_1_delay_wreq <= wr_req_d0;
wr_ack_int <= rf1_ch_1_delay_wack;
when "1000" =>
when "1000" =>
-- Reg rf2_common
rf2_common_wreq <= wr_req_d0;
wr_ack_int <= rf2_common_wack;
when "1100" =>
when "1100" =>
-- Reg rf2_ch_0_csr
rf2_ch_0_csr_wreq <= wr_req_d0;
wr_ack_int <= rf2_ch_0_csr_wack;
when "1101" =>
when "1101" =>
-- Reg rf2_ch_0_delay
rf2_ch_0_delay_wreq <= wr_req_d0;
wr_ack_int <= rf2_ch_0_delay_wack;
when "1110" =>
when "1110" =>
-- Reg rf2_ch_1_csr
rf2_ch_1_csr_wreq <= wr_req_d0;
wr_ack_int <= rf2_ch_1_csr_wack;
when "1111" =>
when "1111" =>
-- Reg rf2_ch_1_delay
rf2_ch_1_delay_wreq <= wr_req_d0;
wr_ack_int <= rf2_ch_1_delay_wack;
......@@ -405,52 +405,52 @@ begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(4 downto 1) is
when "0000" =>
when "0000" =>
-- Reg rf1_common
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf1_common_mixer_en_reg;
rd_dat_d0(2 downto 1) <= rf1_common_mux_sel_reg;
rd_dat_d0(15 downto 3) <= (others => '0');
when "0100" =>
when "0100" =>
-- Reg rf1_ch_0_csr
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf1_ch_0_csr_delay_oen_reg;
rd_dat_d0(1) <= rf1_ch_0_csr_mux_sel_reg;
rd_dat_d0(15 downto 2) <= (others => '0');
when "0101" =>
when "0101" =>
-- Reg rf1_ch_0_delay
rd_ack_d0 <= rd_req_int;
when "0110" =>
when "0110" =>
-- Reg rf1_ch_1_csr
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf1_ch_1_csr_delay_oen_reg;
rd_dat_d0(1) <= rf1_ch_1_csr_mux_sel_reg;
rd_dat_d0(15 downto 2) <= (others => '0');
when "0111" =>
when "0111" =>
-- Reg rf1_ch_1_delay
rd_ack_d0 <= rd_req_int;
when "1000" =>
when "1000" =>
-- Reg rf2_common
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf2_common_mixer_en_reg;
rd_dat_d0(2 downto 1) <= rf2_common_mux_sel_reg;
rd_dat_d0(15 downto 3) <= (others => '0');
when "1100" =>
when "1100" =>
-- Reg rf2_ch_0_csr
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf2_ch_0_csr_delay_oen_reg;
rd_dat_d0(1) <= rf2_ch_0_csr_mux_sel_reg;
rd_dat_d0(15 downto 2) <= (others => '0');
when "1101" =>
when "1101" =>
-- Reg rf2_ch_0_delay
rd_ack_d0 <= rd_req_int;
when "1110" =>
when "1110" =>
-- Reg rf2_ch_1_csr
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= rf2_ch_1_csr_delay_oen_reg;
rd_dat_d0(1) <= rf2_ch_1_csr_mux_sel_reg;
rd_dat_d0(15 downto 2) <= (others => '0');
when "1111" =>
when "1111" =>
-- Reg rf2_ch_1_delay
rd_ack_d0 <= rd_req_int;
when others =>
......
hdl/rtl/wr2rf_rftrigger_regs.vhd
View file @ d82f7502
-- Do not edit. Generated on Wed May 20 15:05:47 2020 by tgingold
-- Do not edit. Generated on Mon Jun 29 17:15:38 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......@@ -200,45 +200,45 @@ begin
t2_we <= '0';
rf_diag_control_wreq <= '0';
case wr_adr_d0(8 downto 7) is
when "00" =>
when "00" =>
-- Submap t1
t1_we <= wr_req_d0;
wr_ack_int <= t1_wack;
when "01" =>
when "01" =>
-- Submap t2
t2_we <= wr_req_d0;
wr_ack_int <= t2_wack;
when "10" =>
when "10" =>
case wr_adr_d0(6 downto 2) is
when "00000" =>
when "00000" =>
case wr_adr_d0(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_control
rf_diag_control_wreq <= wr_req_d0;
wr_ack_int <= rf_diag_control_wack;
when "1" =>
when "1" =>
-- Reg rf_diag_generation
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "00001" =>
when "00001" =>
case wr_adr_d0(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_freq
wr_ack_int <= wr_req_d0;
when "1" =>
when "1" =>
-- Reg rf_diag_freq
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "00010" =>
when "00010" =>
case wr_adr_d0(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_counter
wr_ack_int <= wr_req_d0;
when "1" =>
when "1" =>
-- Reg rf_diag_counter
wr_ack_int <= wr_req_d0;
when others =>
......@@ -259,54 +259,54 @@ begin
t1_re <= '0';
t2_re <= '0';
case adr_int(8 downto 7) is
when "00" =>
when "00" =>
-- Submap t1
t1_re <= rd_req_int;
rd_dat_d0 <= t1_i.dat(15 downto 0);
rd_ack_d0 <= t1_rack;
when "01" =>
when "01" =>
-- Submap t2
t2_re <= rd_req_int;
rd_dat_d0 <= t2_i.dat(15 downto 0);
rd_ack_d0 <= t2_rack;
when "10" =>
when "10" =>
case adr_int(6 downto 2) is
when "00000" =>
when "00000" =>
case adr_int(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_control
rd_ack_d0 <= rd_req_int;
rd_dat_d0(2 downto 0) <= rf_diag_control_window_reg;
rd_dat_d0(3) <= '0';
rd_dat_d0(4) <= rf_diag_control_enable_reg;
rd_dat_d0(15 downto 5) <= (others => '0');
when "1" =>
when "1" =>
-- Reg rf_diag_generation
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= rf_diag_generation_i;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "00001" =>
when "00001" =>
case adr_int(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_freq
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= rf_diag_freq_i(31 downto 16);
when "1" =>
when "1" =>
-- Reg rf_diag_freq
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= rf_diag_freq_i(15 downto 0);
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "00010" =>
when "00010" =>
case adr_int(1 downto 1) is
when "0" =>
when "0" =>
-- Reg rf_diag_counter
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= rf_diag_counter_i(31 downto 16);
when "1" =>
when "1" =>
-- Reg rf_diag_counter
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= rf_diag_counter_i(15 downto 0);
......
hdl/rtl/wr2rf_vme_regs.vhd
View file @ d82f7502
This diff is collapsed.
hdl/top/wr2rf_vme.vhd
View file @ d82f7502
......@@ -156,10 +156,11 @@ entity wr2rf_vme is
-- timing_io
tmg_clk_i : in std_logic_vector(2 downto 1);
tmg_clk_o : out std_logic_vector(2 downto 1);
tmg_clk_oen_o : out std_logic_vector(2 downto 1);
tmg_clk_oe_n_o : out std_logic_vector(2 downto 1);
tmg_clk_term_en_o : out std_logic_vector(2 downto 1);
tmg_io_b : inout std_logic_vector(4 downto 1);
tmg_io_dir_o : out std_logic;
tmg_io_i : in std_logic_vector(4 downto 1);
tmg_io_o : out std_logic_vector(4 downto 1);
tmg_io_oe_n_o : out std_logic_vector(4 downto 1);
tmg_io_term_en_o : out std_logic_vector(4 downto 1);
-- rf1 iqdac
......@@ -378,15 +379,12 @@ architecture rtl of wr2rf_vme is
signal rf2_vtus_wb_in : t_wishbone_master_in;
signal rf2_vtus_wb_out : t_wishbone_master_out;
-- timing_io
signal tmg_clk_out : std_logic_vector(2 downto 1) := (others => '0'); --FIXME
signal tmg_io_out : std_logic_vector(4 downto 1);
signal tmg_io_in : std_logic_vector(4 downto 1);
signal tmg_io_dir : std_logic;
signal mmcm_shift_incdec : std_logic;
signal mmcm_shift_en : std_logic;
signal mmcm_shift_busy : std_logic;
signal tmg_clk_oe_o : std_logic_vector(2 downto 1);
signal tmg_io_oe_o : std_logic_vector(4 downto 1);
begin
-- Poweron reset.
......@@ -819,7 +817,7 @@ begin
rf_t1_rst_p_o => rf1_t1_rst_p_o,
rf_t1_rst_n_o => rf1_t1_rst_n_o,
rf_t1_start_i => tmg_clk_i(1),
rf_t1_stop_i => tmg_io_in(1),
rf_t1_stop_i => tmg_io_i(1),
rf_t2_clk_p_i => rf1_t2_clk_p_i,
rf_t2_clk_n_i => rf1_t2_clk_n_i,
......@@ -828,7 +826,7 @@ begin
rf_t2_rst_p_o => rf1_t2_rst_p_o,
rf_t2_rst_n_o => rf1_t2_rst_n_o,
rf_t2_start_i => tmg_clk_i(1),
rf_t2_stop_i => tmg_io_in(1),
rf_t2_stop_i => tmg_io_i(1),
rf_clk_bufg_o => rf1_clk_bufg);
......@@ -851,7 +849,7 @@ begin
rf_t1_rst_p_o => rf2_t1_rst_p_o,
rf_t1_rst_n_o => rf2_t1_rst_n_o,
rf_t1_start_i => tmg_clk_i(2),
rf_t1_stop_i => tmg_io_in(2),
rf_t1_stop_i => tmg_io_i(2),
rf_t2_clk_p_i => rf2_t2_clk_p_i,
rf_t2_clk_n_i => rf2_t2_clk_n_i,
......@@ -860,7 +858,7 @@ begin
rf_t2_rst_p_o => rf2_t2_rst_p_o,
rf_t2_rst_n_o => rf2_t2_rst_n_o,
rf_t2_start_i => tmg_clk_i(2),
rf_t2_stop_i => tmg_io_in(2),
rf_t2_stop_i => tmg_io_i(2),
rf_clk_bufg_o => rf2_clk_bufg );
......@@ -907,8 +905,8 @@ begin
tmg_clk_term_en_o => tmg_clk_term_en_o,
tmg_io_term_en_o => tmg_io_term_en_o,
tmg_clk_oe_o => tmg_clk_oen_o,
tmg_io_dir_o => tmg_io_dir,
tmg_clk_oe_o => tmg_clk_oe_o,
tmg_io_oe_o => tmg_io_oe_o,
ext_ref_dir_o => ext_ref_dir_o,
dds_cs_n_o => dds_cs_n_o,
......@@ -949,10 +947,9 @@ begin
);
-- timing_io
tmg_clk_o <= tmg_clk_out;
tmg_io_dir_o <= tmg_io_dir;
tmg_io_out <= "0000";
tmg_io_b <= tmg_io_out when tmg_io_dir = '1' else "ZZZZ";
tmg_io_in <= tmg_io_b when tmg_io_dir = '0' else "0000";
tmg_clk_oe_n_o <= not tmg_clk_oe_o;
tmg_io_oe_n_o <= not tmg_io_oe_o;
tmg_clk_o <= "00";
tmg_io_o <= "0000";
end rtl;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment