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wr2rf-vme
Commit 5fb6c286 authored by John Gill's avatar John Gill
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Added registers for WR RFframe timestamps, atomic updates of IQ phase/ampl… 

Added registers for WR RFframe timestamps, atomic updates of IQ phase/ampl settings and changed 19bit VME access space
parent 08d1bc0b
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hdl/rtl/registers/trigunit_regs.vhd
View file @ 5fb6c286
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- Do not edit. Generated on Mon Sep 06 15:26:43 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 5fb6c286
......@@ -639,6 +639,42 @@ memory-map:
description: Timestamp when the last frame was received from RFFrameTransceiver
width: 32
access: ro
- reg:
name: nco_reset_tai
description: Timestamp TAI for the last RFframe received that asserted nco_reset
width: 64
access: ro
children:
- field:
name: val
range: 39-0
- reg:
name: nco_reset_cycles
description: Timestamp TAI for the last RFframe received that asserted nco_reset
width: 32
access: ro
children:
- field:
name: val
range: 27-0
- reg:
name: tai
description: Timestamp TAI for the last RFframe received
width: 64
access: ro
children:
- field:
name: val
range: 39-0
- reg:
name: cycles
description: Timestamp TAI for the last RFframe received
width: 32
access: ro
children:
- field:
name: val
range: 27-0
- block:
name: wrc
description: WR status and time
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 5fb6c286
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- Do not edit. Generated on Mon Sep 06 15:26:44 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 5fb6c286
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hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 5fb6c286
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- Do not edit. Generated on Mon Sep 06 15:26:44 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
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hdl/rtl/wr2rf_regs_core.vhd
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hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 5fb6c286
......@@ -43,8 +43,8 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
-- g_dpram_initf : string := "";
-- g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -499,7 +499,7 @@ architecture rtl of wr2rf_vme is
signal rf2_t2_stop_sel : std_logic_vector(6 downto 1);
signal pps : std_logic;
signal pps_r : std_logic;
signal pps_r : std_logic;
signal tm_link_up : std_logic;
signal tm_time_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
......@@ -603,6 +603,15 @@ architecture rtl of wr2rf_vme is
signal wrs_frame_rftimestamp_r : std_logic_vector(31 downto 0);
signal wrs_rx_reset_nco_pulse : std_logic;
signal rfframe_nco_reset_tai_r : std_logic_vector(39 downto 0);
signal rfframe_nco_reset_cycles_r : std_logic_vector(27 downto 0);
signal rfframe_tai_r : std_logic_vector(39 downto 0);
signal rfframe_cycles_r : std_logic_vector(27 downto 0);
signal rfframe_nco_reset_tai : std_logic_vector(39 downto 0);
signal rfframe_nco_reset_cycles : std_logic_vector(27 downto 0);
signal rfframe_tai : std_logic_vector(39 downto 0);
signal rfframe_cycles : std_logic_vector(27 downto 0);
signal wb_rfframerxtx_in : t_wishbone_master_in;
signal wb_rfframerxtx_out : t_wishbone_master_out;
......@@ -611,10 +620,22 @@ architecture rtl of wr2rf_vme is
signal wb_rf2_rfnco_in : t_wishbone_master_in;
signal wb_rf2_rfnco_out : t_wishbone_master_out;
signal rf1_iqdac_igain_arm : std_logic_vector(15 downto 0);
signal rf1_iqdac_qgain_arm : std_logic_vector(15 downto 0);
signal rf2_iqdac_igain_arm : std_logic_vector(15 downto 0);
signal rf2_iqdac_qgain_arm : std_logic_vector(15 downto 0);
signal rf1_iqdac_phase_update : std_logic;
signal rf2_iqdac_phase_update : std_logic;
signal rf1_iqdac_igain : std_logic_vector(15 downto 0);
signal rf1_iqdac_qgain : std_logic_vector(15 downto 0);
signal rf2_iqdac_igain : std_logic_vector(15 downto 0);
signal rf2_iqdac_qgain : std_logic_vector(15 downto 0);
signal rf1_iqdac_igain_r : std_logic_vector(15 downto 0);
signal rf1_iqdac_qgain_r : std_logic_vector(15 downto 0);
signal rf2_iqdac_igain_r : std_logic_vector(15 downto 0);
signal rf2_iqdac_qgain_r : std_logic_vector(15 downto 0);
signal rf1_iqdac_ctrl : std_logic_vector(15 downto 0);
signal rf2_iqdac_ctrl : std_logic_vector(15 downto 0);
......@@ -670,7 +691,7 @@ architecture rtl of wr2rf_vme is
attribute keep : string;
attribute IOB of pps_r : signal is "true";
attribute keep of pps_r : signal is "true";
begin
-- Poweron reset.
......@@ -764,7 +785,7 @@ begin
pps_i => pps_p,
pps_valid_i => tm_time_valid,
clk10m_o => clk_ext_10m_o );
------------------------------------------------------------------------------
-- Dedicated clock for GTP
------------------------------------------------------------------------------
......@@ -1023,15 +1044,23 @@ begin
begin
if rising_edge (clk_sys_62m5) then
if rst_sys_n = '0' then
wrs_frame_counter_r <= (others => '0');
wrs_frame_counter_r <= (others => '0');
wrs_frame_rxwrtimestamp_r <= (others => '0');
wrs_frame_txwrtimestamp_r <= (others => '0');
wrs_frame_rftimestamp_r <= (others => '0');
wrs_frame_rftimestamp_r <= (others => '0');
rfframe_nco_reset_tai_r <= (others => '0');
rfframe_nco_reset_cycles_r <= (others => '0');
rfframe_tai_r <= (others => '0');
rfframe_cycles_r <= (others => '0');
else
wrs_frame_counter_r <= wrs_frame_counter;
wrs_frame_counter_r <= wrs_frame_counter;
wrs_frame_rxwrtimestamp_r <= wrs_frame_rxwrtimestamp;
wrs_frame_txwrtimestamp_r <= wrs_frame_txwrtimestamp;
wrs_frame_rftimestamp_r <= wrs_frame_rftimestamp;
rfframe_nco_reset_tai_r <= rfframe_nco_reset_tai;
rfframe_nco_reset_cycles_r <= rfframe_nco_reset_cycles;
rfframe_tai_r <= rfframe_tai;
rfframe_cycles_r <= rfframe_cycles;
end if;
end if;
end process;
......@@ -1052,6 +1081,12 @@ begin
wrs_frame_rxwrtimestamp <= tm_tai(3 downto 0) & tm_cycles when wrs_rx_valid_r = '1' else wrs_frame_rxwrtimestamp_r;
wrs_frame_rftimestamp <= tm_tai(3 downto 0) & tm_cycles when wrs_frame_valid = '1' else wrs_frame_rftimestamp_r;
rfframe_nco_reset_tai <= tm_tai when wrs_rx_reset_nco_pulse = '1' else rfframe_nco_reset_tai_r;
rfframe_nco_reset_cycles <= tm_cycles when wrs_rx_reset_nco_pulse = '1' else rfframe_nco_reset_cycles_r;
rfframe_tai <= tm_tai when wrs_frame_valid = '1' else rfframe_tai_r;
rfframe_cycles <= tm_cycles when wrs_frame_valid = '1' else rfframe_cycles_r;
loc_rx_RFmFramePayloads.control(0) <= loc_nco_ctrl_reset;
loc_rx_RFmFramePayloads.FTW_H1_main <= loc_nco_h1_ftw;
loc_rx_RFmFramePayloads.FTW_H1_prog <= loc_nco_h1_prog;
......@@ -1083,10 +1118,27 @@ begin
dds_sync_p_o => dds_sync_p_o,
dds_sync_n_o => dds_sync_n_o );
rf1_iqdac_igain <= rf1_iqdac_igain_arm when rf1_iqdac_phase_update = '1' else rf1_iqdac_igain_r;
rf1_iqdac_qgain <= rf1_iqdac_qgain_arm when rf1_iqdac_phase_update = '1' else rf1_iqdac_qgain_r;
rf2_iqdac_igain <= rf2_iqdac_igain_arm when rf2_iqdac_phase_update = '1' else rf2_iqdac_igain_r;
rf2_iqdac_qgain <= rf2_iqdac_qgain_arm when rf2_iqdac_phase_update = '1' else rf2_iqdac_qgain_r;
process (clk_sys_62m5) is
begin
if rising_edge(clk_sys_62m5) then
dds_ioupdate_r <= dds_ioupdate or nco_reset_dds;
if (rst_sys = '1') then
dds_ioupdate_r <= '0';
rf1_iqdac_igain_r <= (others => '0');
rf1_iqdac_qgain_r <= (others => '0');
rf2_iqdac_igain_r <= (others => '0');
rf2_iqdac_qgain_r <= (others => '0');
else
dds_ioupdate_r <= dds_ioupdate or nco_reset_dds;
rf1_iqdac_igain_r <= rf1_iqdac_igain;
rf1_iqdac_qgain_r <= rf1_iqdac_qgain;
rf2_iqdac_igain_r <= rf2_iqdac_igain;
rf2_iqdac_qgain_r <= rf2_iqdac_qgain;
end if;
end if;
end process;
......@@ -1228,7 +1280,7 @@ begin
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID,
g_DECODER => (0 => (adem => x"fff00000", amcap => x"ee000000_00000000", dawpr => x"83"),
g_DECODER => (0 => (adem => x"fff80000", amcap => x"ee000000_00000000", dawpr => x"83"),
others => (adem => x"00000000", amcap => x"00000000_00000000", dawpr => x"83")) )
port map (
clk_i => clk_sys_62m5,
......@@ -1443,10 +1495,16 @@ begin
wb_rf2_rfnco_i => wb_rf2_rfnco_in,
wb_rf2_rfnco_o => wb_rf2_rfnco_out,
rf1_iqdac_igain_o => rf1_iqdac_igain,
rf1_iqdac_qgain_o => rf1_iqdac_qgain,
rf2_iqdac_igain_o => rf2_iqdac_igain,
rf2_iqdac_qgain_o => rf2_iqdac_qgain,
rf1_iqdac_phase_update_o => rf1_iqdac_phase_update,
rf2_iqdac_phase_update_o => rf2_iqdac_phase_update,
rf1_iqdac_igain_arm_o => rf1_iqdac_igain_arm,
rf1_iqdac_qgain_arm_o => rf1_iqdac_qgain_arm,
rf2_iqdac_igain_arm_o => rf2_iqdac_igain_arm,
rf2_iqdac_qgain_arm_o => rf2_iqdac_qgain_arm,
rf1_iqdac_igain_i => rf1_iqdac_igain_r,
rf1_iqdac_qgain_i => rf1_iqdac_qgain_r,
rf2_iqdac_igain_i => rf2_iqdac_igain_r,
rf2_iqdac_qgain_i => rf2_iqdac_qgain_r,
rf1_iqdac_ctrl_o => rf1_iqdac_ctrl,
rf2_iqdac_ctrl_o => rf2_iqdac_ctrl,
iqdac_ram_write_o => iqdac_ram_write,
......@@ -1536,12 +1594,16 @@ begin
loc_nco_update_valid_o => loc_nco_update_valid,
loc_or_wrs_params_sel_o => loc_or_wrs_params_sel,
wrs_frame_last_ftw_i => wrs_rx_RFmFramePayloads.FTW_H1_main,
wrs_frame_last_ctrl_i => wrs_rx_RFmFramePayloads.control,
wrs_frame_last_ftw_i => wrs_rx_RFmFramePayloads.FTW_H1_main,
wrs_frame_last_ctrl_i => wrs_rx_RFmFramePayloads.control,
wrs_frame_last_rxwrtimestamp_i => wrs_frame_rxwrtimestamp_r,
wrs_frame_last_txwrtimestamp_i => wrs_frame_txwrtimestamp_r,
wrs_frame_last_rftimestamp_i => wrs_frame_rftimestamp_r,
wrs_frame_counter_i => std_logic_vector(wrs_frame_counter_r),
wrs_frame_last_rftimestamp_i => wrs_frame_rftimestamp_r,
wrs_frame_counter_i => std_logic_vector(wrs_frame_counter_r),
rfframe_nco_reset_tai_i => rfframe_nco_reset_tai,
rfframe_nco_reset_cycles_i => rfframe_nco_reset_cycles,
rfframe_tai_i => rfframe_tai,
rfframe_cycles_i => rfframe_cycles,
txframe_payload_o => wrs_tx_RFmFramePayloads,
......
software/include/wr2rf_init_regs.h
View file @ 5fb6c286
......@@ -2,8 +2,8 @@
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "oc_spi16_regs.h"
#include "wr2rf_init_rf_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
/* RF indentification */
......
software/include/wr2rf_rfnco_regs.h
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software/include/wr2rf_rftrigger_regs.h
View file @ 5fb6c286
#ifndef __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#define __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#include "trigunit_regs.h"
#include "vtudiag_regs.h"
#include "trigunit_regs.h"
#define WR2RF_RFTRIGGER_REGS_SIZE 272 /* 0x110 */
/* None */
......
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