Added registers for atomic updates to iqdac IQ amplitude and phase functions.

08d1bc0b · John Gill · bf56e518 · 08d1bc0b · 08d1bc0b · 08d1bc0b
Commit 08d1bc0b authored Sep 01, 2021 by John Gill
10 changed files
--- a/hdl/rtl/registers/trigunit_regs.vhd
+++ b/hdl/rtl/registers/trigunit_regs.vhd
-- Do not edit.  Generated on Fri Apr 16 10:16:55 2021 by jgill
+-- Do not edit.  Generated on Wed Sep 01 09:30:11 2021 by jgill
 -- With Cheby 1.4.dev0 and these options:
 --  -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd


--- a/hdl/rtl/registers/wr2rf_ctrl_regs.cheby
+++ b/hdl/rtl/registers/wr2rf_ctrl_regs.cheby
@@ -25,25 +25,79 @@ memory-map:
     size: 4096
     x-hdl: 
      busgroup: true
+  - reg:
+     name: rf1_iqdac_phase
+     description: phase represented as a signed integer
+     access: rw
+     width: 16
+  - reg:
+     name: rf2_iqdac_phase
+     description: phase represented as a signed integer
+     access: rw
+     width: 16
+  - reg:
+     name: rf1_iqdac_phase_update
+     description: phase represented as a signed integer
+     access: rw
+     width: 16
+     children:
+     - field:
+        name: valid
+        range: 0
+        preset: 0
+        x-hdl:
+         type: autoclear
+  - reg:
+     name: rf2_iqdac_phase_update
+     description: phase represented as a signed integer
+     access: rw
+     width: 16
+     children:
+     - field:
+        name: valid
+        range: 0
+        preset: 0
+        x-hdl:
+         type: autoclear
+  - reg:
+     name: rf1_iqdac_igain_arm
+     description: I ampl/phase for IQ complex multiplier
+     access: rw
+     width: 16
+  - reg:
+     name: rf1_iqdac_qgain_arm
+     description: Q ampl/phase for IQ complex multiplier
+     access: rw
+     width: 16
+  - reg:
+     name: rf2_iqdac_igain_arm
+     description: I ampl/phase for IQ complex multiplier
+     access: rw
+     width: 16
+  - reg:
+     name: rf2_iqdac_qgain_arm
+     description: Q ampl/phase for IQ complex multiplier
+     access: rw
+     width: 16
  - reg:
     name: rf1_iqdac_igain
     description: I gain for IQ complex multiplier
-     access: rw
+     access: ro
     width: 16
  - reg:
     name: rf1_iqdac_qgain
     description: I gain for IQ complex multiplier
-     access: rw
+     access: ro
     width: 16
  - reg:
     name: rf2_iqdac_igain
     description: I gain for IQ complex multiplier
-     access: rw
+     access: ro
     width: 16
  - reg:
     name: rf2_iqdac_qgain
     description: I gain for IQ complex multiplier
-     access: rw
+     access: ro
     width: 16
  - reg:
     name: rf1_iqdac_ctrl

--- a/hdl/rtl/registers/wr2rf_init_rf_regs.vhd
+++ b/hdl/rtl/registers/wr2rf_init_rf_regs.vhd
-- Do not edit.  Generated on Fri Apr 16 10:16:56 2021 by jgill
+-- Do not edit.  Generated on Wed Sep 01 09:30:11 2021 by jgill
 -- With Cheby 1.4.dev0 and these options:
 --  -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd


--- a/hdl/rtl/registers/wr2rf_rfnco_regs.vhd
+++ b/hdl/rtl/registers/wr2rf_rfnco_regs.vhd
-- Do not edit.  Generated on Fri Apr 16 10:16:57 2021 by jgill
+-- Do not edit.  Generated on Wed Sep 01 09:30:12 2021 by jgill
 -- With Cheby 1.4.dev0 and these options:
 --  -i RFNCO.cheby --gen-hdl


--- a/hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
+++ b/hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
-- Do not edit.  Generated on Fri Apr 16 10:16:56 2021 by jgill
+-- Do not edit.  Generated on Wed Sep 01 09:30:11 2021 by jgill
 -- With Cheby 1.4.dev0 and these options:
 --  -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd


--- a/hdl/rtl/registers/wr2rf_vme_regs.vhd
+++ b/hdl/rtl/registers/wr2rf_vme_regs.vhd
--- a/software/include/wr2rf_ctrl_regs.h
+++ b/software/include/wr2rf_ctrl_regs.h
@@ -2,7 +2,7 @@
 #define __CHEBY__WR2RF_CTRL_REGS__H__

 #include "wr2rf_rftrigger_regs.h"
-#define WR2RF_CTRL_REGS_SIZE 12338 /* 0x3032 */
+#define WR2RF_CTRL_REGS_SIZE 12354 /* 0x3042 */

 /* Registers for rf1 vtus */
 #define WR2RF_CTRL_REGS_RF1_VTUS 0x0UL
@@ -20,50 +20,76 @@
 #define WR2RF_CTRL_REGS_RF2_RFNCO 0x2000UL
 #define WR2RF_CTRL_REGS_RF2_RFNCO_SIZE 4096 /* 0x1000 = 4KB */

+/* phase represented as a signed integer */
+#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE 0x3000UL
+
+/* phase represented as a signed integer */
+#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE 0x3002UL
+
+/* phase represented as a signed integer */
+#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE 0x3004UL
+#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE_VALID 0x1UL
+
+/* phase represented as a signed integer */
+#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE 0x3006UL
+#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE_VALID 0x1UL
+
+/* I ampl/phase for IQ complex multiplier */
+#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN_ARM 0x3008UL
+
+/* Q ampl/phase for IQ complex multiplier */
+#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN_ARM 0x300aUL
+
+/* I ampl/phase for IQ complex multiplier */
+#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN_ARM 0x300cUL
+
+/* Q ampl/phase for IQ complex multiplier */
+#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN_ARM 0x300eUL
+
 /* I gain for IQ complex multiplier */
-#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN 0x3000UL
+#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN 0x3010UL

 /* I gain for IQ complex multiplier */
-#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN 0x3002UL
+#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN 0x3012UL

 /* I gain for IQ complex multiplier */
-#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN 0x3004UL
+#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN 0x3014UL

 /* I gain for IQ complex multiplier */
-#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN 0x3006UL
+#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN 0x3016UL

 /* Select iqdac I + Q sources */
-#define WR2RF_CTRL_REGS_RF1_IQDAC_CTRL 0x3008UL
+#define WR2RF_CTRL_REGS_RF1_IQDAC_CTRL 0x3018UL

 /* Select iqdac I + Q sources */
-#define WR2RF_CTRL_REGS_RF2_IQDAC_CTRL 0x300aUL
+#define WR2RF_CTRL_REGS_RF2_IQDAC_CTRL 0x301aUL

 /* Select iqdac ram address */
-#define WR2RF_CTRL_REGS_IQDAC_RAM_ADDR 0x300cUL
+#define WR2RF_CTRL_REGS_IQDAC_RAM_ADDR 0x301cUL

 /* iqdac ram data to be written at address iqdac_ram_addr */
-#define WR2RF_CTRL_REGS_IQDAC_RAM_DATA 0x300eUL
+#define WR2RF_CTRL_REGS_IQDAC_RAM_DATA 0x301eUL

 /* Some magic controls bit tbd */
-#define WR2RF_CTRL_REGS_IQDAC_RAM_WRITE 0x3010UL
+#define WR2RF_CTRL_REGS_IQDAC_RAM_WRITE 0x3020UL

 /* Some magic controls bit tbd */
-#define WR2RF_CTRL_REGS_IQDAC_RAM_PLAY 0x3012UL
+#define WR2RF_CTRL_REGS_IQDAC_RAM_PLAY 0x3022UL

 /* None */
-#define WR2RF_CTRL_REGS_RF1_DDS_FTW_VALID 0x3014UL
+#define WR2RF_CTRL_REGS_RF1_DDS_FTW_VALID 0x3024UL

 /* Phase increment value to xilinx dds core */
-#define WR2RF_CTRL_REGS_RF1_DDS_FTW 0x3018UL
+#define WR2RF_CTRL_REGS_RF1_DDS_FTW 0x3028UL

 /* None */
-#define WR2RF_CTRL_REGS_RF2_DDS_FTW_VALID 0x3020UL
+#define WR2RF_CTRL_REGS_RF2_DDS_FTW_VALID 0x3030UL

 /* Phase increment value to xilinx dds core */
-#define WR2RF_CTRL_REGS_RF2_DDS_FTW 0x3028UL
+#define WR2RF_CTRL_REGS_RF2_DDS_FTW 0x3038UL

 /* Configures behaviour for how an nco_reset will operate */
-#define WR2RF_CTRL_REGS_NCO_RESET_CTRL 0x3030UL
+#define WR2RF_CTRL_REGS_NCO_RESET_CTRL 0x3040UL
 #define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_DDS 0x1UL
 #define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH1 0x2UL
 #define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH2 0x4UL
@@ -90,55 +116,79 @@ struct wr2rf_ctrl_regs {
  /* [0x2000]: SUBMAP Registers for rf2 rfnco */
  uint32_t rf2_rfnco[1024];

-  /* [0x3000]: REG (rw) I gain for IQ complex multiplier */
+  /* [0x3000]: REG (rw) phase represented as a signed integer */
+  uint16_t rf1_iqdac_phase;
+
+  /* [0x3002]: REG (rw) phase represented as a signed integer */
+  uint16_t rf2_iqdac_phase;
+
+  /* [0x3004]: REG (rw) phase represented as a signed integer */
+  uint16_t rf1_iqdac_phase_update;
+
+  /* [0x3006]: REG (rw) phase represented as a signed integer */
+  uint16_t rf2_iqdac_phase_update;
+
+  /* [0x3008]: REG (rw) I ampl/phase for IQ complex multiplier */
+  uint16_t rf1_iqdac_igain_arm;
+
+  /* [0x300a]: REG (rw) Q ampl/phase for IQ complex multiplier */
+  uint16_t rf1_iqdac_qgain_arm;
+
+  /* [0x300c]: REG (rw) I ampl/phase for IQ complex multiplier */
+  uint16_t rf2_iqdac_igain_arm;
+
+  /* [0x300e]: REG (rw) Q ampl/phase for IQ complex multiplier */
+  uint16_t rf2_iqdac_qgain_arm;
+
+  /* [0x3010]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf1_iqdac_igain;

-  /* [0x3002]: REG (rw) I gain for IQ complex multiplier */
+  /* [0x3012]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf1_iqdac_qgain;

-  /* [0x3004]: REG (rw) I gain for IQ complex multiplier */
+  /* [0x3014]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf2_iqdac_igain;

-  /* [0x3006]: REG (rw) I gain for IQ complex multiplier */
+  /* [0x3016]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf2_iqdac_qgain;

-  /* [0x3008]: REG (rw) Select iqdac I + Q sources */
+  /* [0x3018]: REG (rw) Select iqdac I + Q sources */
  uint16_t rf1_iqdac_ctrl;

-  /* [0x300a]: REG (rw) Select iqdac I + Q sources */
+  /* [0x301a]: REG (rw) Select iqdac I + Q sources */
  uint16_t rf2_iqdac_ctrl;

-  /* [0x300c]: REG (rw) Select iqdac ram address */
+  /* [0x301c]: REG (rw) Select iqdac ram address */
  uint16_t iqdac_ram_addr;

-  /* [0x300e]: REG (rw) iqdac ram data to be written at address iqdac_ram_addr */
+  /* [0x301e]: REG (rw) iqdac ram data to be written at address iqdac_ram_addr */
  uint16_t iqdac_ram_data;

-  /* [0x3010]: REG (rw) Some magic controls bit tbd */
+  /* [0x3020]: REG (rw) Some magic controls bit tbd */
  uint16_t iqdac_ram_write;

-  /* [0x3012]: REG (rw) Some magic controls bit tbd */
+  /* [0x3022]: REG (rw) Some magic controls bit tbd */
  uint16_t iqdac_ram_play;

-  /* [0x3014]: REG (rw) (no description) */
+  /* [0x3024]: REG (rw) (no description) */
  uint16_t rf1_dds_ftw_valid;

-  /* padding to: 12312 words */
+  /* padding to: 12328 words */
  uint8_t __padding_2[2];

-  /* [0x3018]: REG (rw) Phase increment value to xilinx dds core */
+  /* [0x3028]: REG (rw) Phase increment value to xilinx dds core */
  uint64_t rf1_dds_ftw;

-  /* [0x3020]: REG (rw) (no description) */
+  /* [0x3030]: REG (rw) (no description) */
  uint16_t rf2_dds_ftw_valid;

-  /* padding to: 12328 words */
+  /* padding to: 12344 words */
  uint8_t __padding_3[6];

-  /* [0x3028]: REG (rw) Phase increment value to xilinx dds core */
+  /* [0x3038]: REG (rw) Phase increment value to xilinx dds core */
  uint64_t rf2_dds_ftw;

-  /* [0x3030]: REG (rw) Configures behaviour for how an nco_reset will operate */
+  /* [0x3040]: REG (rw) Configures behaviour for how an nco_reset will operate */
  uint16_t nco_reset_ctrl;
 };


--- a/software/include/wr2rf_init_regs.h
+++ b/software/include/wr2rf_init_regs.h
@@ -2,8 +2,8 @@
 #define __CHEBY__WR2RF_INIT_REGS__H__

 #include "oc_spi16_regs.h"
-#include "hwInfo.h"
 #include "wr2rf_init_rf_regs.h"
+#include "hwInfo.h"
 #define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */

 /* RF indentification */

--- a/software/include/wr2rf_rftrigger_regs.h
+++ b/software/include/wr2rf_rftrigger_regs.h
 #ifndef __CHEBY__WR2RF_RFTRIGGER_REGS__H__
 #define __CHEBY__WR2RF_RFTRIGGER_REGS__H__

-#include "vtudiag_regs.h"
 #include "trigunit_regs.h"
+#include "vtudiag_regs.h"
 #define WR2RF_RFTRIGGER_REGS_SIZE 272 /* 0x110 */

 /* None */

--- a/software/include/wr2rf_vme_regs.h
+++ b/software/include/wr2rf_vme_regs.h
@@ -21,7 +21,7 @@ struct wr2rf_vme_regs {
  struct wr2rf_ctrl_regs ctrl;

  /* padding to: 16384 words */
-  uint8_t __padding_0[4046];
+  uint8_t __padding_0[4030];
 };

 #endif /* __CHEBY__WR2RF_VME_REGS__H__ */