vtuCore: renaming.

46d11795 · Tristan Gingold · 0a61c042 · 46d11795
Commit 46d11795 authored Apr 23, 2020 by Tristan Gingold
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Showing with 27 additions and 27 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +27 -27

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1238,7 +1238,7 @@ architecture vtuCore of vtuCore is
  signal SwitchtoHT : std_logic;
  signal wValue_effective : std_logic_vector(63 downto 0 );
  signal Shifter1Ena : std_logic;
-  signal DataOut_2 : std_logic_vector(7 downto 0 );
+  signal DataOut_HT : std_logic_vector(7 downto 0 );
  signal HTSwitchEna : std_logic;
  signal PulseCount : std_logic_vector(63 downto 0 );
  signal SetStartData : std_logic := '0';
@@ -1281,15 +1281,15 @@ architecture vtuCore of vtuCore is
  signal PlayingMem : std_logic;
  signal Stop_seq : std_logic;
  signal Start_seq : std_logic;
-  signal DataOut_1 : std_logic_vector(7 downto 0 );
+  signal DataOut_B : std_logic_vector(7 downto 0 );
  signal SetPlayingMem : std_logic;
  signal PlayingMem_i : std_logic;
  signal MemAddrIsZero : std_logic;
  signal FirstSyncArrived : std_logic := '0';
  signal Mem_AddrZero : std_logic_vector(14 downto 0 );
  signal Mem_RdData_prev : std_logic_vector(7 downto 0 ) := (others  => '0');
-  signal OE_1 : std_logic;
-  signal OE_2 : std_logic;
+  signal OE_B : std_logic;
+  signal OE_HT : std_logic;
  signal MemAddrIsZeroPrev : std_logic;
  signal StartPlayMem : std_logic;
  signal RunPlayAndSyncPulse : std_logic;
@@ -1302,8 +1302,8 @@ begin
    generic map (N => 64,
                 g_DisableDoubleSync => '1')
    port map (CoarseZero => BCoarseZero,
-              DataOut => DataOut_1,
-              OutputEnabled => OE_1,
+              DataOut => DataOut_B,
+              OutputEnabled => OE_B,
              Clk => Clk,
              Delay => bValue,
              DataIn => DataIn,
@@ -1315,8 +1315,8 @@ begin
    generic map (N => 64,
                 g_DisableDoubleSync => '0')
    port map (CoarseZero => HTCoarseZero,
-              DataOut => DataOut_2,
-              OutputEnabled => OE_2,
+              DataOut => DataOut_HT,
+              OutputEnabled => OE_HT,
              Clk => Clk,
              Delay => htValue_effective,
              DataIn => DataIn_2,
@@ -1335,8 +1335,8 @@ begin
              Start => Start_seq,
              Stop => Stop_seq,
              SyncPulse => SyncPulse_i,
-              OutputEnable1 => OE_1,
-              OutputEnable2 => OE_2,
+              OutputEnable1 => OE_B,
+              OutputEnable2 => OE_HT,
              Shifter1Ena => Shifter1Ena,
              Shifter2Ena => Shifter2Ena,
              SwitchtoHT => SwitchtoHT,
@@ -1456,15 +1456,15 @@ begin

  SwitchOutput <= SwitchtoHT or (not Run_seq);

-  process (DataOut_1, DataOut_2, SwitchOutput)
+  process (DataOut_B, DataOut_HT, SwitchOutput)
  begin
    case SwitchOutput is
      when '0' =>
        --  B datashifter.
-        DataOut_seq_i <=  DataOut_1;
+        DataOut_seq_i <=  DataOut_B;
      when others =>
        --  HT datashifter
-        DataOut_seq_i <=  DataOut_2;
+        DataOut_seq_i <=  DataOut_HT;
    end case;
  end process;

@@ -1472,15 +1472,15 @@ begin

  DataOut_seq <=  DataOut_seq_i when RstOrStopSeq = '0' else (others => '0');

-  process (DataOut_1, DataOut_2, SwitchtoHT)
+  process (DataOut_B, DataOut_HT, SwitchtoHT)
  begin
    case SwitchtoHT is
      when '0' =>
        --  B datashifter to HT datashifter
-        DataIn_2 <=  DataOut_1;
+        DataIn_2 <=  DataOut_B;
      when others =>
        --  HT datashifter loopback.
-        DataIn_2 <=  DataOut_2;
+        DataIn_2 <=  DataOut_HT;
    end case;
  end process;

@@ -1502,7 +1502,7 @@ begin
     end case;
   end process;

-  HTSwitchEna <= (OE_2 or OE_SyncLess) and htSwitching;
+  HTSwitchEna <= (OE_HT or OE_SyncLess) and htSwitching;

  process (Clk, Run_i)
  begin
@@ -1557,7 +1557,7 @@ begin
      end if;
  end process;

-  counterEnable <= (OE_1 or OE_2) and Run_seq;
+  counterEnable <= (OE_B or OE_HT) and Run_seq;

  wValueOne_seq <= (wValueOne or SinglePulseMode) and (not InfiniteWindow);

@@ -1682,7 +1682,7 @@ begin

  RunPlayAndSyncPulse <= RunPlayMem and SyncPulse_i;

-  SetPlayingMem <= FirstSyncArrived and OE_1;
+  SetPlayingMem <= FirstSyncArrived and OE_B;

  PlayingMem <= (PlayingMem_i or SetPlayingMem) and (not StopPlayMem);

@@ -1733,14 +1733,14 @@ begin
    end if;
  end process;

-  FirstBit <= "000" when FirstOutput='1' and DataOut_1(0)='1' else
-              "001" when FirstOutput='1' and DataOut_1(1)='1' else
-              "010" when FirstOutput='1' and DataOut_1(2)='1' else
-              "011" when FirstOutput='1' and DataOut_1(3)='1' else
-              "100" when FirstOutput='1' and DataOut_1(4)='1' else
-              "101" when FirstOutput='1' and DataOut_1(5)='1' else
-              "110" when FirstOutput='1' and DataOut_1(6)='1' else
-              "111" when FirstOutput='1' and DataOut_1(7)='1' else
+  FirstBit <= "000" when FirstOutput='1' and DataOut_B(0)='1' else
+              "001" when FirstOutput='1' and DataOut_B(1)='1' else
+              "010" when FirstOutput='1' and DataOut_B(2)='1' else
+              "011" when FirstOutput='1' and DataOut_B(3)='1' else
+              "100" when FirstOutput='1' and DataOut_B(4)='1' else
+              "101" when FirstOutput='1' and DataOut_B(5)='1' else
+              "110" when FirstOutput='1' and DataOut_B(6)='1' else
+              "111" when FirstOutput='1' and DataOut_B(7)='1' else
              "000";

  ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;