vtuCore: improve style.

0a61c042 · Tristan Gingold · c6c9cdcb · 0a61c042
Commit 0a61c042 authored Apr 23, 2020 by Tristan Gingold
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Showing with 7 additions and 7 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +7 -7

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1358,11 +1358,11 @@ begin
    generic map (N => 64,
                 g_DisableDoubleSync => '0')
    port map (CoarseZero => open,
-              DataOut => DataOutHTSyncLess(7 downto 0),
+              DataOut => DataOutHTSyncLess,
              OutputEnabled => OE_SyncLess,
              Clk => Clk,
-              Delay => htValue_effective(63 downto 0),
-              DataIn => DataInHTSyncLess(7 downto 0),
+              Delay => htValue_effective,
+              DataIn => DataInHTSyncLess,
              Enabled => SyncLessEna,
              SyncPulse => open);

@@ -1502,10 +1502,12 @@ begin
     end case;
   end process;

+  HTSwitchEna <= (OE_2 or OE_SyncLess) and htSwitching;
+
  process (Clk, Run_i)
  begin
-   if Run_i = '0' then
-     SwitchHTeffective <= '0';
+    if Run_i = '0' then
+      SwitchHTeffective <= '0';
    elsif Clk'event and Clk = '1' then
      if HTSwitchEna = '1' then
        SwitchHTeffective <= not SwitchHTeffective;
@@ -1515,8 +1517,6 @@ begin

  COne(63 downto 0) <= (0=> '1', others => '0');

-  HTSwitchEna <= (OE_2 or OE_SyncLess) and htSwitching;
-
  process (Clk)
  begin
    if Clk'event and Clk = '1' then