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Commit 3ddd5ae0 authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: improve style.

parent 5995be54
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Showing with 47 additions and 50 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ 3ddd5ae0
......@@ -1249,7 +1249,6 @@ architecture vtuCore of vtuCore is
signal wrongW_s : std_logic;
signal WindowedOperationMode : std_logic;
signal DataOutPulse : std_logic;
signal NoStart : std_logic;
signal InfiniteWindowMode : std_logic;
signal DataFilled : std_logic_vector(7 downto 0 );
signal HTCoarseZero : std_logic;
......@@ -1446,6 +1445,12 @@ begin
wrongValue <= wrongB_s or wrongHT_s or wrongW_s;
wrongB <= wrongB_s;
wrongHT <= wrongHT_s;
wrongW <= wrongW_s;
Stop_seq <= Stop or wrongValue;
process (Start, SyncPulse_i, UseSyncAsStart)
......@@ -1458,26 +1463,52 @@ begin
end case;
end process;
wrongB <= wrongB_s;
wrongHT <= wrongHT_s;
wrongW <= wrongW_s;
process (Start_i, NoStart, DisconnectStart)
process (Start_i, DisconnectStart)
begin
case DisconnectStart is
when '0' =>
Start_seq <= Start_i;
when others =>
Start_seq <= NoStart;
Start_seq <= '0';
end case;
end process;
NoStart <= '0';
Run_i <= Run_seq or RunSyncLess or PlayingMem;
process (DataOut_1, DataOut_2, SwitchOutput)
begin
case SwitchOutput is
when '0' =>
-- B datashifter.
DataOut_seq_i <= DataOut_1;
when others =>
-- HT datashifter
DataOut_seq_i <= DataOut_2;
end case;
end process;
process (DataOut_seq_i, RstOrStopSeq)
begin
case RstOrStopSeq is
when '0' =>
DataOut_seq <= DataOut_seq_i;
when others =>
DataOut_seq <= (others => '0');
end case;
end process;
process (DataOut_1, DataOut_2, SwitchtoHT)
begin
case SwitchtoHT is
when '0' =>
-- B datashifter to HT datashifter
DataIn_2 <= DataOut_1;
when others =>
-- HT datashifter loopback.
DataIn_2 <= DataOut_2;
end case;
end process;
DataOut <= DataOutHTSyncLess when Mode = C_Code_ctuAsVtu_control2_mode_syncLessOperation else
DataOutLowFreq when Mode = C_Code_ctuAsVtu_control2_mode_lowFreqGeneration else
DataOutPlayMem when Mode = C_Code_ctuAsVtu_control2_mode_playMemory else
......@@ -1520,30 +1551,6 @@ begin
Run <= Run_i;
process (DataOut_1, DataOut_2, SwitchOutput)
begin
case SwitchOutput is
when '0' =>
-- B datashifter.
DataOut_seq_i <= DataOut_1;
when others =>
-- HT datashifter
DataOut_seq_i <= DataOut_2;
end case;
end process;
process (DataOut_1, DataOut_2, SwitchtoHT)
begin
case SwitchtoHT is
when '0' =>
-- B datashifter to HT datashifter
DataIn_2 <= DataOut_1;
when others =>
-- HT datashifter loopback.
DataIn_2 <= DataOut_2;
end case;
end process;
process (Clk)
begin
if Clk'event and Clk = '1' then
......@@ -1557,10 +1564,10 @@ begin
process (PulseCount , wValue_effective)
begin
if ((PulseCount(63 downto 0)) = (wValue_effective(63 downto 0))) then
if PulseCount = wValue_effective then
WindowDone <= '1';
else
if (unsigned((PulseCount(63 downto 0))) < unsigned((wValue_effective(63 downto 0)))) then
if unsigned(PulseCount) < unsigned(wValue_effective) then
WindowDone <= '0';
else
WindowDone <= '1';
......@@ -1568,7 +1575,7 @@ begin
end if;
end process;
process (wValue_effective, CZero)
process (wValue_effective)
begin
if wValue_effective = (63 downto 0 => '0') then
wValueOne <= '1';
......@@ -1577,9 +1584,9 @@ begin
end if;
end process;
process (CZero, wValue)
process (wValue)
begin
if CZero(63 downto 0) = wValue(63 downto 0) then
if wValue = (63 downto 0 => '0') then
wValueZero <= '1';
else
wValueZero <= '0';
......@@ -1598,16 +1605,6 @@ begin
InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode;
process (DataOut_seq_i, AllZeroOut, RstOrStopSeq)
begin
case RstOrStopSeq is
when '0' =>
DataOut_seq(7 downto 0) <= DataOut_seq_i(7 downto 0);
when others =>
DataOut_seq(7 downto 0) <= AllZeroOut(7 downto 0);
end case;
end process;
process (DataOutHTSyncLess , SyncLessStartData , SetStartData)
begin
case SetStartData is
......
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