Commit 5995be54 authored by Tristan Gingold's avatar Tristan Gingold

vtuCore: simplify HDL.

parent a86114d3
......@@ -1304,10 +1304,6 @@ architecture vtuCore of vtuCore is
signal RunPlayMem_i : std_logic;
signal ReadDataZero : std_logic;
signal visual_B_PulseCounter_cur_state : std_logic_vector(64 - 1 downto 0 );
signal visual_B_PulseCounter_next_state : std_logic_vector(64 - 1 downto 0 );
signal visual_B_PulseCounter_next_count : std_logic_vector(64 - 1 downto 0 );
signal visual_B_PulseCounter_en_state : std_logic_vector(64 - 1 downto 0 );
signal visual_B_ClkValueSwitchFF_Q : std_logic;
signal visual_B_SwitchHTFF_Q : std_logic;
......@@ -1548,33 +1544,17 @@ begin
end case;
end process;
PulseCount(63 downto 0) <= visual_B_PulseCounter_cur_state;
visual_B_PulseCounter_en_state <= visual_B_PulseCounter_next_count
when counterEnable = '1'
else visual_B_PulseCounter_cur_state;
visual_B_PulseCounter_next_state <= visual_B_PulseCounter_en_state;
process (Clk)
begin
if Clk'event and Clk = '1' then
if counterReset = '1' then
visual_B_PulseCounter_cur_state <= (others => '0');
else
visual_B_PulseCounter_cur_state <= visual_B_PulseCounter_next_state;
PulseCount <= (others => '0');
elsif counterEnable = '1' then
PulseCount <= std_logic_vector(unsigned (PulseCount) + 1);
end if;
end if;
end process;
process (visual_B_PulseCounter_cur_state )
variable plus_minus_one : unsigned(64 - 1 downto 0);
begin
plus_minus_one := "0000000000000000000000000000000000000000000000000000000000000001" ;
visual_B_PulseCounter_next_count <=
std_logic_vector(unsigned (visual_B_PulseCounter_cur_state) + plus_minus_one);
end process;
process (PulseCount , wValue_effective)
begin
if ((PulseCount(63 downto 0)) = (wValue_effective(63 downto 0))) then
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment