VTU timestamp fix

2ca38be9 · John Gill · cfa9dbec · 2ca38be9 · 2ca38be9
Commit 2ca38be9 authored Apr 03, 2023 by John Gill
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Showing with 6 additions and 3 deletions

iqdac_io.vhd hdl/rtl/iqdac_io.vhd +3 -0

vtu_blk.vhd hdl/rtl/vtu_blk.vhd +3 -3

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--- a/hdl/rtl/iqdac_io.vhd
+++ b/hdl/rtl/iqdac_io.vhd
@@ -36,6 +36,9 @@ architecture rtl of iqdac_io is
    
 begin

+    -- Look. I and Q are _inverted_. The RF mixer post IQ DAC
+    -- is an upside conversion to 247(=223.5+23.5) MHz. We need
+    -- the downside conversion, so invert I and Q to the IQ DAC.
    dac_qdata <= '1' & iqdac_qdata_i;
    dac_idata <= '0' & iqdac_idata_i;    
    

--- a/hdl/rtl/vtu_blk.vhd
+++ b/hdl/rtl/vtu_blk.vhd
@@ -758,7 +758,7 @@ begin
       begin
          if (rising_edge(clk_vtu_x2_i)) then
             sync_data_oserdes_r <= sync_data_oserdes;
-             vtu_trig_redge_r         <= vtu_trig_redge;
+             vtu_trig_redge_r    <= vtu_trig_redge;
          end if;
       end process;

@@ -775,6 +775,7 @@ begin
       process (clk_sys_i) is
       begin
          if (rising_edge(clk_sys_i)) then
+             first_vtu_trig_active_r <= first_vtu_trig_active;             
             if vtu_trig_redge_sys = '1' then
                last_vtu_trig_tai_sec_r    <= X"000000" & tm_tai_i;
                last_vtu_trig_tai_cycles_r <= X"0"      & tm_cycles_i;
@@ -782,8 +783,7 @@ begin
                   first_vtu_trig_tai_sec_r    <= X"000000" & tm_tai_i;
                   first_vtu_trig_tai_cycles_r <= X"0"      & tm_cycles_i;
                end if;
-                first_vtu_trig_active_r <= first_vtu_trig_active;
-                end if; 
+             end if; 
          end if;
       end process;