vtuCore: simplify HDL.

c6c9cdcb · Tristan Gingold · 483953bb · c6c9cdcb
Commit c6c9cdcb authored Apr 23, 2020 by Tristan Gingold
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Showing with 9 additions and 24 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +9 -24

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1220,8 +1220,6 @@ architecture vtuCore of vtuCore is
  signal DataOut_seq_i : std_logic_vector(7 downto 0 );
  signal RunSyncLess : std_logic;
  signal wrongValue : std_logic;
-  signal SwitchHTeffective_n : std_logic;
-  signal ClkValueSwitch_n : std_logic;
  signal SyncLessEna : std_logic;
  signal DataOutLowFreq : std_logic_vector(7 downto 0 );
  signal DataIn_2 : std_logic_vector(7 downto 0 );
@@ -1298,9 +1296,6 @@ architecture vtuCore of vtuCore is
  signal RunPlayMem_i : std_logic;
  signal ReadDataZero : std_logic;

-  signal visual_B_ClkValueSwitchFF_Q : std_logic;
-  signal visual_B_SwitchHTFF_Q : std_logic;
-
 begin
  --  Data shifter using B parameters: from Sync pulse to the first pulse.
  B_DataShifterB: entity work.vtuDataShifter
@@ -1507,16 +1502,13 @@ begin
     end case;
   end process;

-  SwitchHTeffective <= visual_B_SwitchHTFF_Q;
-  SwitchHTeffective_n <= not visual_B_SwitchHTFF_Q;
-
  process (Clk, Run_i)
  begin
   if Run_i = '0' then
-      visual_B_SwitchHTFF_Q <= '0';
+     SwitchHTeffective <= '0';
    elsif Clk'event and Clk = '1' then
      if HTSwitchEna = '1' then
-        visual_B_SwitchHTFF_Q <= SwitchHTeffective_n;
+        SwitchHTeffective <= not SwitchHTeffective;
      end if;
    end if;
  end process;
@@ -1538,17 +1530,15 @@ begin

  process (PulseCount, wValue_effective)
  begin
-    if PulseCount = wValue_effective then
-      WindowDone <= '1';
+    if unsigned(PulseCount) < unsigned(wValue_effective) then
+      WindowDone <= '0';
    else
-      if unsigned(PulseCount) < unsigned(wValue_effective) then
-        WindowDone <= '0';
-      else
-        WindowDone <= '1';
-      end if;
+      WindowDone <= '1';
    end if;
  end process;

+  WindowDone_seq <= WindowDone and (not InfiniteWindow);
+
  process (wValue_effective)
   begin
      if wValue_effective = (63 downto 0 => '0') then
@@ -1567,8 +1557,6 @@ begin
      end if;
  end process;

-  WindowDone_seq <= WindowDone and (not InfiniteWindow);
-
  counterEnable <= (OE_1 or OE_2) and Run_seq;

  wValueOne_seq <= (wValueOne or SinglePulseMode) and (not InfiniteWindow);
@@ -1589,16 +1577,13 @@ begin

  SyncLessDisabled <= not SyncLessEna;

-  ClkValueSwitch <= visual_B_ClkValueSwitchFF_Q;
-  ClkValueSwitch_n <= not visual_B_ClkValueSwitchFF_Q;
-
  process (Clk , RstOrStopSeq)
  begin
    if RstOrStopSeq = '1' then
-      visual_B_ClkValueSwitchFF_Q <= '0';
+      ClkValueSwitch <= '0';
    elsif (Clk'event and Clk = '1') then
      if DataOutPulse = '1' then
-        visual_B_ClkValueSwitchFF_Q <= ClkValueSwitch_n;
+        ClkValueSwitch <= not ClkValueSwitch;
      end if;
    end if;
  end process;