Merge branch 'integrate_rt_software' into v3-rc2

rt/.gitignore

+*.bin
+*.elf
+*.o
+*.sh
+*.stp
+revision.*
\ No newline at end of file

rt/Makefile

+CROSS_COMPILE ?= lm32-elf-
+
+LIBSOFTPLL_DIR = ../userspace/ptp-noposix/softpll
+
+OBJS = main.o dev/uart.o dev/timer.o lib/mprintf.o dev/ad9516.o ipc/minipc-mem-server.o ipc/rt_ipc.o $(LIBSOFTPLL_DIR)/softpll_ng.o
+
+CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -Idev
+LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled   -nostdlib -T target/lm32/ram.ld 
+OBJS_PLATFORM=target/lm32/crt0.o target/lm32/irq.o
+
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+CFLAGS= $(CFLAGS_PLATFORM) -ffunction-sections -fdata-sections -O3 -Iinclude -include include/trace.h  -ffreestanding -Iipc -I$(LIBSOFTPLL_DIR) -I.
+LDFLAGS= $(LDFLAGS_PLATFORM) -Wl,--gc-sections -O3 -Iinclude -ffreestanding 
+SIZE = $(CROSS_COMPILE)size
+OBJS += $(OBJS_PLATFORM)
+REVISION=$(shell git rev-parse HEAD)
+
+OUTPUT=rt_cpu
+
+all: 		$(OBJS)
+				$(SIZE) -t $(OBJS)
+				echo "const char *build_revision = \"$(REVISION)\";" > revision.c
+				echo "const char *build_date = __DATE__ \" \" __TIME__;" >> revision.c
+				$(CC) $(CFLAGS) -c revision.c
+				${CC} -o $(OUTPUT).elf $(OBJS) revision.o $(LDFLAGS) 
+				${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
+
+clean:	
+				rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram
+
+scp:		all
+				scp rt_cpu.bin root@pcbe12132:/tftpboot/rootfs/wr/lib/firmware
+
+%.o:		%.c
+				${CC} $(CFLAGS) $(LIB_DIR) -c $^ -o $@
+

rt/dev/ad9516.c

+/*
+ * Trivial pll programmer using an spi controoler.
+ * PLL is AD9516, SPI is opencores
+ * Tomasz Wlostowski, Alessandro Rubini, 2011, for CERN.
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "board.h"
+#include "timer.h"
+#include "gpio.h"
+
+
+#include "ad9516.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+#endif
+
+struct ad9516_reg {
+	uint16_t reg;
+	uint8_t val;
+};
+
+#include "ad9516_config.h"
+
+/*
+ * SPI stuff, used by later code
+ */
+
+#define SPI_REG_RX0	0
+#define SPI_REG_TX0	0
+#define SPI_REG_RX1	4
+#define SPI_REG_TX1	4
+#define SPI_REG_RX2	8
+#define SPI_REG_TX2	8
+#define SPI_REG_RX3	12
+#define SPI_REG_TX3	12
+
+#define SPI_REG_CTRL	16
+#define SPI_REG_DIVIDER	20
+#define SPI_REG_SS	24
+
+#define SPI_CTRL_ASS		(1<<13)
+#define SPI_CTRL_IE		(1<<12)
+#define SPI_CTRL_LSB		(1<<11)
+#define SPI_CTRL_TXNEG		(1<<10)
+#define SPI_CTRL_RXNEG		(1<<9)
+#define SPI_CTRL_GO_BSY		(1<<8)
+#define SPI_CTRL_CHAR_LEN(x)	((x) & 0x7f)
+
+#define GPIO_PLL_RESET_N 1
+#define GPIO_SYS_CLK_SEL 0
+#define GPIO_PERIPH_RESET_N 3
+
+#define CS_PLL	0 /* AD9516 on SPI CS0 */
+
+static void *oc_spi_base;
+
+int oc_spi_init(void *base_addr)
+{
+	oc_spi_base = base_addr;
+
+	writel(100, oc_spi_base + SPI_REG_DIVIDER);
+	return 0;
+}
+
+int oc_spi_txrx(int ss, int nbits, uint32_t in, uint32_t *out)
+{
+	uint32_t rval;
+
+	if (!out)
+		out = &rval;
+
+	writel(SPI_CTRL_ASS | SPI_CTRL_CHAR_LEN(nbits)
+		     | SPI_CTRL_TXNEG,
+		     oc_spi_base + SPI_REG_CTRL);
+
+	writel(in, oc_spi_base + SPI_REG_TX0);
+	writel((1 << ss), oc_spi_base + SPI_REG_SS);
+	writel(SPI_CTRL_ASS | SPI_CTRL_CHAR_LEN(nbits)
+		     | SPI_CTRL_TXNEG | SPI_CTRL_GO_BSY,
+		     oc_spi_base + SPI_REG_CTRL);
+
+	while(readl(oc_spi_base + SPI_REG_CTRL) & SPI_CTRL_GO_BSY)
+		;
+	*out = readl(oc_spi_base + SPI_REG_RX0);
+	return 0;
+}
+
+/*
+ * AD9516 stuff, using SPI, used by later code.
+ * "reg" is 12 bits, "val" is 8 bits, but both are better used as int
+ */
+
+static void ad9516_write_reg(int reg, int val)
+{
+	oc_spi_txrx(CS_PLL, 24, (reg << 8) | val, NULL);
+}
+
+static int ad9516_read_reg(int reg)
+{
+	uint32_t rval;
+	oc_spi_txrx(CS_PLL, 24, (reg << 8) | (1 << 23), &rval);
+	return rval & 0xff;
+}
+
+
+
+static void ad9516_load_regset(const struct ad9516_reg *regs, int n_regs, int commit)
+{
+	int i;
+	for(i=0; i<n_regs; i++)
+		ad9516_write_reg(regs[i].reg, regs[i].val);
+		
+	if(commit)
+		ad9516_write_reg(0x232, 1);
+}
+
+
+static void ad9516_wait_lock()
+{
+	while ((ad9516_read_reg(0x1f) & 1) == 0);
+}
+
+#define SECONDARY_DIVIDER 0x100
+
+int ad9516_set_output_divider(int output, int ratio, int phase_offset)
+{
+	uint8_t lcycles = (ratio/2) - 1;
+	uint8_t hcycles = (ratio - (ratio / 2)) - 1;
+	int secondary = (output & SECONDARY_DIVIDER) ? 1 : 0;
+	output &= 0xf;
+
+	if(output >= 0 && output < 6) /* LVPECL outputs */
+	{
+		uint16_t base = (output / 2) * 0x3 + 0x190;
+
+		if(ratio == 1)  /* bypass the divider */
+		{
+			uint8_t div_ctl = ad9516_read_reg(base + 1);
+			ad9516_write_reg(base + 1, div_ctl | (1<<7) | (phase_offset & 0xf)); 
+		} else {
+			uint8_t div_ctl = ad9516_read_reg(base + 1);
+			TRACE("DivCtl: %x\n", div_ctl);
+			ad9516_write_reg(base + 1, (div_ctl & (~(1<<7))) | (phase_offset & 0xf));  /* disable bypass bit */
+			ad9516_write_reg(base, (lcycles << 4) | hcycles);
+		}
+	} else { /* LVDS/CMOS outputs */
+			
+		uint16_t base = ((output - 6) / 2) * 0x5 + 0x199;
+
+		TRACE("Output [divider %d]: %d ratio: %d base %x lc %d hc %d\n", secondary, output, ratio, base, lcycles ,hcycles);
+
+		if(!secondary)
+		{
+			if(ratio == 1)  /* bypass the divider 1 */
+				ad9516_write_reg(base + 3, ad9516_read_reg(base + 3) | 0x10); 
+			else {
+				ad9516_write_reg(base, (lcycles << 4) | hcycles); 
+				ad9516_write_reg(base + 1, phase_offset & 0xf);
+			}
+		} else {
+			if(ratio == 1)  /* bypass the divider 2 */
+				ad9516_write_reg(base + 3, ad9516_read_reg(base + 3) | 0x20); 
+			else {
+				ad9516_write_reg(base + 2, (lcycles << 4) | hcycles); 
+//				ad9516_write_reg(base + 1, phase_offset & 0xf);
+				
+		}
+		}		
+	}
+
+	/* update */
+	ad9516_write_reg(0x232, 0x0);
+	ad9516_write_reg(0x232, 0x1);
+	ad9516_write_reg(0x232, 0x0);
+
+}
+
+int ad9516_set_vco_divider(int ratio) /* Sets the VCO divider (2..6) or 0 to enable static output */
+{
+	if(ratio == 0)
+		ad9516_write_reg(0x1e0, 0x5); /* static mode */
+	else
+		ad9516_write_reg(0x1e0, (ratio-2));
+	ad9516_write_reg(0x232, 0x1);
+}
+
+void ad9516_sync_outputs()
+{
+	/* VCO divider: static mode */
+	ad9516_write_reg(0x1E0, 0x7);
+	ad9516_write_reg(0x232, 0x1);
+
+	/* Sync the outputs when they're inactive to avoid +-1 cycle uncertainity */
+	ad9516_write_reg(0x230, 1);
+	ad9516_write_reg(0x232, 1);
+	ad9516_write_reg(0x230, 0);
+	ad9516_write_reg(0x232, 1);
+}
+
+int ad9516_init(int ref_source)
+{
+	TRACE("Initializing AD9516 PLL...\n");
+
+	oc_spi_init((void *)BASE_SPI);
+
+	gpio_out(GPIO_SYS_CLK_SEL, 0); /* switch to the standby reference clock, since the PLL is off after reset */
+
+	/* reset the PLL */
+	gpio_out(GPIO_PLL_RESET_N, 0);
+	timer_delay(10);
+	gpio_out(GPIO_PLL_RESET_N, 1);
+	timer_delay(10);
+	
+	/* Use unidirectional SPI mode */
+	ad9516_write_reg(0x000, 0x99);
+
+	/* Check the presence of the chip */
+	if (ad9516_read_reg(0x3) != 0xc3) {
+		TRACE("Error: AD9516 PLL not responding.\n");
+		return -1;
+	}
+
+	ad9516_load_regset(ad9516_base_config, ARRAY_SIZE(ad9516_base_config), 0);
+	ad9516_load_regset(ad9516_ref_tcxo, ARRAY_SIZE(ad9516_ref_tcxo), 1);
+	ad9516_wait_lock();
+
+	ad9516_sync_outputs();
+	ad9516_set_output_divider(9, 4, 0);  /* AUX/SWCore = 187.5 MHz */
+	ad9516_set_output_divider(7, 12, 0); /* REF = 62.5 MHz */
+	ad9516_set_output_divider(4, 12, 0);  /* GTX = 62.5 MHz */
+	ad9516_sync_outputs();
+	ad9516_set_vco_divider(2); 
+	
+	TRACE("AD9516 locked.\n");
+
+	gpio_out(GPIO_SYS_CLK_SEL, 1); /* switch the system clock to the PLL reference */
+	gpio_out(GPIO_PERIPH_RESET_N, 0); /* reset all peripherals which use AD9516-provided clocks */
+	gpio_out(GPIO_PERIPH_RESET_N, 1);
+
+	return 0;
+}
+

rt/dev/ad9516_config.h

+
+/* Base configuration (global dividers, output config, reference-independent) */
+const struct ad9516_reg ad9516_base_config[] = {
+{0x0000, 0x99},
+{0x0001, 0x00},
+{0x0002, 0x10},
+{0x0003, 0xC3},
+{0x0004, 0x00},
+{0x0010, 0x7C},
+{0x0011, 0x05},
+{0x0012, 0x00},
+{0x0013, 0x0C},
+{0x0014, 0x12},
+{0x0015, 0x00},
+{0x0016, 0x05},
+{0x0017, 0x88},
+{0x0018, 0x07},
+{0x0019, 0x00},
+{0x001A, 0x00},
+{0x001B, 0x00},
+{0x001C, 0x02},
+{0x001D, 0x00},
+{0x001E, 0x00},
+{0x001F, 0x0E},
+{0x00A0, 0x01},
+{0x00A1, 0x00},
+{0x00A2, 0x00},
+{0x00A3, 0x01},
+{0x00A4, 0x00},
+{0x00A5, 0x00},
+{0x00A6, 0x01},
+{0x00A7, 0x00},
+{0x00A8, 0x00},
+{0x00A9, 0x01},
+{0x00AA, 0x00},
+{0x00AB, 0x00},
+{0x00F0, 0x0A},
+{0x00F1, 0x0A},
+{0x00F2, 0x0A},
+{0x00F3, 0x0A},
+{0x00F4, 0x08},
+{0x00F5, 0x08},
+{0x0140, 0x43},
+{0x0141, 0x42},
+{0x0142, 0x43},
+{0x0143, 0x42},
+{0x0190, 0x00},
+{0x0191, 0x80},
+{0x0192, 0x00},
+{0x0193, 0xBB},
+{0x0194, 0x00},
+{0x0195, 0x00},
+{0x0196, 0x00},
+{0x0197, 0x00},
+{0x0198, 0x00},
+{0x0199, 0x11},
+{0x019A, 0x00},
+{0x019B, 0x11},
+{0x019C, 0x20},
+{0x019D, 0x00},
+{0x019E, 0x11},
+{0x019F, 0x00},
+{0x01A0, 0x11},
+{0x01A1, 0x20},
+{0x01A2, 0x00},
+{0x01A3, 0x00},
+{0x01E0, 0x04},
+{0x01E1, 0x02},
+{0x0230, 0x00},
+{0x0231, 0x00},
+};
+
+/* Config for 25 MHz VCTCXO reference (RDiv = 5, use REF1) */
+const struct ad9516_reg ad9516_ref_tcxo[] = {
+{0x0011, 0x05},
+{0x0012, 0x00}, /* RDiv = 5 */
+{0x001C, 0x06}  /* Use REF1 */
+};
+
+/* Config for 10 MHz external reference (RDiv = 2, use REF2) */
+const struct ad9516_reg ad9516_ref_ext[] = {
+{0x0011, 0x02},
+{0x0012, 0x00}, /* RDiv = 2 */
+{0x001C, 0x46}  /* Use REF1 */
+};
+

rt/dev/ad9516_regs.h

+const struct {int reg; uint8_t val} ad9516_regs[] = {
+{0x0000, 0x99},
+{0x0001, 0x00},
+{0x0002, 0x10},
+{0x0003, 0xC3},
+{0x0004, 0x00},
+{0x0010, 0x7C},
+{0x0011, 0x01},
+{0x0012, 0x00},
+{0x0013, 0x04},
+{0x0014, 0x07},
+{0x0015, 0x00},
+{0x0016, 0x04},
+{0x0017, 0x00},
+{0x0018, 0x07},
+{0x0019, 0x00},
+{0x001A, 0x00},
+{0x001B, 0x00},
+{0x001C, 0x02},
+{0x001D, 0x00},
+{0x001E, 0x00},
+{0x001F, 0x0E},
+{0x00A0, 0x01},
+{0x00A1, 0x00},
+{0x00A2, 0x00},
+{0x00A3, 0x01},
+{0x00A4, 0x00},
+{0x00A5, 0x00},
+{0x00A6, 0x01},
+{0x00A7, 0x00},
+{0x00A8, 0x00},
+{0x00A9, 0x01},
+{0x00AA, 0x00},
+{0x00AB, 0x00},
+{0x00F0, 0x0A},
+{0x00F1, 0x0A},
+{0x00F2, 0x0A},
+{0x00F3, 0x0A},
+{0x00F4, 0x08},
+{0x00F5, 0x0A},
+{0x0140, 0x43},
+{0x0141, 0x43},
+{0x0142, 0x43},
+{0x0143, 0x43},
+{0x0190, 0x00},
+{0x0191, 0x80},
+{0x0192, 0x00},
+{0x0193, 0xBB},
+{0x0194, 0x00},
+{0x0195, 0x00},
+{0x0196, 0x00},
+{0x0197, 0x00},
+{0x0198, 0x00},
+{0x0199, 0x22},
+{0x019A, 0x00},
+{0x019B, 0x11},
+{0x019C, 0x00},
+{0x019D, 0x00},
+{0x019E, 0x22},
+{0x019F, 0x00},
+{0x01A0, 0x11},
+{0x01A1, 0x00},
+{0x01A2, 0x00},
+{0x01A3, 0x00},
+{0x01E0, 0x04},
+{0x01E1, 0x02},
+{0x0230, 0x00},
+{0x0231, 0x00},
+{0x0232, 0x00},
+{-1, 0}};

rt/dev/timer.c

+#include "board.h"
+
+#include "timer.h"
+
+uint32_t timer_get_tics()
+{
+  return *(volatile uint32_t *) (BASE_TIMER);
+}
+
+void timer_delay(uint32_t how_long)
+{
+  uint32_t t_start;
+
+  t_start = timer_get_tics();
+
+	if(t_start + how_long < t_start)
+		while(t_start + how_long < timer_get_tics());
+
+	while(t_start + how_long > timer_get_tics());
+}

rt/dev/uart.c

+#include "defs.h"
+#include "board.h"
+#include "uart.h"
+
+#include <hw/wb_uart.h>
+
+#define CALC_BAUD(baudrate) \
+    ( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
+      (CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
+
+static volatile struct UART_WB *uart = (volatile struct UART_WB *) BASE_UART;
+
+void uart_init()
+{
+	uart->BCR = CALC_BAUD(UART_BAUDRATE);
+}
+
+void uart_write_byte(int b)
+{
+	if(b == '\n')
+		uart_write_byte('\r');
+	while(uart->SR & UART_SR_TX_BUSY)
+		;
+	uart->TDR = b;
+}
+
+void uart_write_string(char *s)
+{
+	while (*s)
+		uart_write_byte(*(s++));
+}
+
+int uart_poll()
+{
+ 	return uart->SR & UART_SR_RX_RDY;
+}
+
+int uart_read_byte()
+{
+ 	return uart ->RDR & 0xff;
+}
\ No newline at end of file

rt/include/board.h

+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* RT CPU Memory layout */
+
+#define CPU_CLOCK 62500000
+
+#define UART_BAUDRATE 115200
+
+#define BASE_UART 0x10000
+#define BASE_SOFTPLL 0x10100
+#define BASE_SPI 0x10200
+#define BASE_GPIO 0x10300
+#define BASE_TIMER 0x10400
+#define BASE_PPS_GEN 0x10500
+
+#endif

rt/include/defs.h

+#ifndef __DEFS_H
+#define __DEFS_H
+
+#include <stdint.h>
+
+static inline void writel(uint32_t data, void *where)
+{
+	* (volatile uint32_t *)where = data;
+}
+
+static inline uint32_t readl(void *where)
+{
+	return * (volatile uint32_t *)where;
+}
+
+
+#endif

rt/include/gpio.h

+#ifndef __GPIO_H
+#define __GPIO_H
+
+#include <stdint.h>
+
+#include "board.h"
+
+struct GPIO_WB
+{
+  uint32_t CODR;  /*Clear output register*/
+  uint32_t SODR;  /*Set output register*/
+  uint32_t DDR;   /*Data direction register (1 means out)*/
+  uint32_t PSR;   /*Pin state register*/
+};
+
+static volatile struct GPIO_WB *__gpio = (volatile struct GPIO_WB *) BASE_GPIO;
+
+static inline void gpio_out(int pin, int val)
+{
+  if(val)
+    __gpio->SODR = (1<<pin);
+  else
+    __gpio->CODR = (1<<pin);
+}
+
+static inline void gpio_dir(int pin, int val)
+{
+  if(val)
+    __gpio->DDR |= (1<<pin);
+  else
+    __gpio->DDR &= ~(1<<pin);
+}
+
+static inline int gpio_in(int bank, int pin)
+{
+  return __gpio->PSR & (1<<pin) ? 1: 0;
+}
+
+        
+#endif
+        

rt/include/hw/wb_uart.h

+/*
+  Register definitions for slave core: Simple Wishbone UART
+
+  * File           : ../../../../software/include/hw/wb_uart.h
+  * Author         : auto-generated by wbgen2 from uart.wb
+  * Created        : Mon Feb 21 22:25:02 2011
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_UART_WB
+#define __WBGEN2_REGDEFS_UART_WB
+
+#include <stdint.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Status Register */
+
+/* definitions for field: TX busy in reg: Status Register */
+#define UART_SR_TX_BUSY                       WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: RX ready in reg: Status Register */
+#define UART_SR_RX_RDY                        WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Baudrate control register */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for field: Transmit data in reg: Transmit data regsiter */
+#define UART_TDR_TX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_TDR_TX_DATA_SHIFT                0
+#define UART_TDR_TX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_TDR_TX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for field: Received data in reg: Receive data regsiter */
+#define UART_RDR_RX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_RDR_RX_DATA_SHIFT                0
+#define UART_RDR_RX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_RDR_RX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+/* [0x0]: REG Status Register */
+#define UART_REG_SR 0x00000000
+/* [0x4]: REG Baudrate control register */
+#define UART_REG_BCR 0x00000004
+/* [0x8]: REG Transmit data regsiter */
+#define UART_REG_TDR 0x00000008
+/* [0xc]: REG Receive data regsiter */
+#define UART_REG_RDR 0x0000000c
+
+PACKED struct UART_WB {
+  /* [0x0]: REG Status Register */
+  uint32_t SR;
+  /* [0x4]: REG Baudrate control register */
+  uint32_t BCR;
+  /* [0x8]: REG Transmit data regsiter */
+  uint32_t TDR;
+  /* [0xc]: REG Receive data regsiter */
+  uint32_t RDR;
+};
+
+#endif

rt/include/irq.h

+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline void clear_irq()
+{
+  unsigned int val = 1;
+  asm volatile ("wcsr ip, %0"::"r"(val));
+}
+
+#endif

rt/include/stdint.h

+#ifndef __ARCH_LM32_STDINT_H__
+#define __ARCH_LM32_STDINT_H__
+
+/*
+ * We miss a stdint.h in our compiler, so provide some types here,
+ * knowing the CPU is 32-bits and uses LP32 model
+ */
+
+typedef unsigned char	uint8_t;
+typedef unsigned short	uint16_t;
+typedef unsigned long	uint32_t;
+typedef unsigned long	long uint64_t;
+
+typedef signed char	int8_t;
+typedef signed short	int16_t;
+typedef signed long	int32_t;
+typedef signed long	long int64_t;
+
+#endif /* __ARCH_LM32_STDINT_H__ */

rt/include/timer.h

+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include "defs.h"
+
+#define TICS_PER_SECOND 100000
+
+uint32_t timer_get_tics();
+void timer_delay(uint32_t how_long);
+int timer_expired(uint32_t t_start, uint32_t how_long);
+
+#endif

rt/include/trace.h

+#ifndef __FREESTANDING_TRACE_H__
+#define __FREESTANDING_TRACE_H__
+
+int mprintf(char const *format, ...);
+
+#define TRACE(...) mprintf(__VA_ARGS__)
+#define TRACE_DEV(...) mprintf(__VA_ARGS__)
+
+#endif

rt/include/uart.h

+#ifndef __UART_H
+#define __UART_H
+
+int mprintf(char const *format, ...);
+
+void uart_init();
+void uart_write_byte(int b);
+void uart_write_string(char *s);
+int uart_poll();
+int uart_read_byte();
+
+#endif

rt/ipc/minipc-int.h

+/*
+ * Private definition for mini-ipc
+ *
+ * Copyright (C) 2011 CERN (www.cern.ch)
+ * Author: Alessandro Rubini <rubini@gnudd.com>
+ * Based on ideas by Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ */
+#ifndef __MINIPC_INT_H__
+#define __MINIPC_INT_H__
+
+#include <sys/types.h>
+#if __STDC_HOSTED__ /* freestanding servers have less material */
+#include <sys/un.h>
+#include <sys/select.h>
+#endif
+
+#include "minipc.h"
+
+/*  be safe, in case some other header had them slightly differntly */
+#undef container_of
+#undef offsetof
+#undef ARRAY_SIZE
+
+/* We are strongly based on container_of internally */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+/*
+ * While public symbols are minipc_* internal ones are mpc_* to be shorter.
+ * The connection includes an fd, which is the only thing returned back
+ */
+
+/* The list of functions attached to a service */
+struct mpc_flist {
+	const struct minipc_pd *pd;
+	struct mpc_flist *next;
+};
+
+/*
+ * The main server or client structure. Server links have client sockets
+ * hooking on it.
+ */
+struct mpc_link {
+	struct minipc_ch ch;
+	int magic;
+	int pid;
+	int flags;
+	struct mpc_link *nextl;
+	struct mpc_flist *flist;
+	void *memaddr;
+	int memsize;
+#if __STDC_HOSTED__ /* these fields are not used in freestanding uC */
+	FILE *logf;
+	struct sockaddr_un addr;
+	int fd[MINIPC_MAX_CLIENTS];
+	fd_set fdset;
+#endif
+	char name[MINIPC_MAX_NAME];
+};
+#define MPC_MAGIC		0xc0ffee99
+
+#define MPC_FLAG_SERVER		0x00010000
+#define MPC_FLAG_CLIENT		0x00020000
+#define MPC_FLAG_SHMEM		0x00040000
+#define MPC_FLAG_DEVMEM		0x00080000
+#define MPC_USER_FLAGS(x)	((x) & 0xffff)
+
+/* The request packet being transferred */
+struct mpc_req_packet {
+	char name[MINIPC_MAX_NAME];
+	uint32_t args[MINIPC_MAX_ARGUMENTS];
+};
+/* The reply packet being transferred */
+struct mpc_rep_packet {
+	uint32_t type;
+	uint8_t val[MINIPC_MAX_REPLY];
+};
+
+/* A structure for shared memory (takes more than 2kB) */
+struct mpc_shmem {
+	uint32_t	nrequest;	/* incremented at each request */
+	uint32_t	nreply;		/* incremented at each reply */
+	struct mpc_req_packet	request;
+	struct mpc_rep_packet	reply;
+};
+
+#define MPC_TIMEOUT		1000 /* msec, hardwired */
+
+static inline struct mpc_link *mpc_get_link(struct minipc_ch *ch)
+{
+	return container_of(ch, struct mpc_link, ch);
+}
+
+#define CHECK_LINK(link) /* Horrible shortcut, don't tell around... */	\
+	if ((link)->magic != MPC_MAGIC) {				\
+		errno = EINVAL;						\
+		return -1;						\
+	}
+
+extern struct mpc_link *__mpc_base;
+extern void mpc_free_flist(struct mpc_link *link, struct mpc_flist *flist);
+
+extern struct minipc_ch *__minipc_link_create(const char *name, int flags);
+
+/* Used for lists and structures -- sizeof(uint32_t) is 4, is it? */
+#define MINIPC_GET_ANUM(len) (((len) + 3) >> 2)
+
+
+#endif /* __MINIPC_INT_H__ */

rt/ipc/minipc-mem-server.c

+/*
+ * Mini-ipc: Exported functions for freestanding server
+ *
+ * Copyright (C) 2012 CERN (www.cern.ch)
+ * Author: Alessandro Rubini <rubini@gnudd.com>
+ *
+ * This replicates some code of minipc-core and minipc-server.
+ * It implements the functions needed to make a freestanding server
+ * (for example, an lm32 running on an FPGA -- the case I actually need).
+ */
+
+#include "minipc-int.h"
+#include <string.h>
+#include <sys/errno.h>
+
+/* HACK: use a static link, one only */
+static struct mpc_link __static_link;
+
+/* The create function just picks an hex address from the name "mem:AABBCC" */
+struct minipc_ch *minipc_server_create(const char *name, int flags)
+{
+	struct mpc_link *link = &__static_link;
+	int i, c, addr = 0;
+	int memsize = sizeof(struct mpc_shmem);
+
+	if (link->magic) {
+		errno = EBUSY;
+		return NULL;
+	}
+
+	/* Most code from __minipc_link_create and __minipc_memlink_create */
+	flags |= MPC_FLAG_SERVER;
+
+	if (strncmp(name, "mem:", 4)) {
+		errno = EINVAL;
+		return NULL;
+	}
+
+	/* Ok, valid name. Hopefully */
+	link->magic = MPC_MAGIC;
+	link->flags = flags;
+	strncpy(link->name, name, sizeof(link->name) -1);
+
+	/* Parse the hex address */
+	for (i = 4; (c = name[i]); i++) {
+		addr *= 0x10;
+		if (c >= '0' && c <= '9') addr += c - '0';
+		if (c >= 'a' && c <= 'f') addr += c - 'a' + 10;
+		if (c >= 'A' && c <= 'F') addr += c - 'A' + 10;
+	}
+	link->flags |= MPC_FLAG_SHMEM; /* needed? */
+
+	link->memaddr = (void *)addr;
+	link->memsize = memsize;
+	link->pid = 0; /* hack: nrequest */
+	if (link->flags & MPC_FLAG_SERVER)
+		memset(link->memaddr, 0, memsize);
+
+	return &link->ch;
+}
+
+/* Close only marks the link as available */
+int minipc_close(struct minipc_ch *ch)
+{
+	struct mpc_link *link = mpc_get_link(ch);
+	CHECK_LINK(link);
+	link->magic = 0; /* available */
+	return 0;
+}
+
+/* HACK: use a static array of flist, to avoid malloc and free */
+static struct mpc_flist __static_flist[MINIPC_MAX_EXPORT];
+
+static void *calloc(size_t unused, size_t unused2)
+{
+	int i;
+	struct mpc_flist *p;
+
+	for (p = __static_flist, i = 0; i < MINIPC_MAX_EXPORT; p++, i++)
+		if (!p->pd)
+			break;
+	if (i == MINIPC_MAX_EXPORT) {
+		errno = ENOMEM;
+		return NULL;
+	}
+	return p;
+}
+
+static void free(void *ptr)
+{
+	struct mpc_flist *p = ptr;
+	p->pd = NULL;
+}
+
+
+/* From: minipc-core.c, but relying on fake free above */
+void mpc_free_flist(struct mpc_link *link, struct mpc_flist *flist)
+{
+	struct mpc_flist **nextp;
+
+	/* Look for flist and release it*/
+	for (nextp = &link->flist; (*nextp); nextp = &(*nextp)->next)
+		if (*nextp == flist)
+			break;
+	if (!*nextp) {
+		return;
+	}
+	*nextp = flist->next;
+	free(flist);
+}
+
+
+/* From: minipc-server.c -- but no log and relies on fake calloc above */
+int minipc_export(struct minipc_ch *ch, const struct minipc_pd *pd)
+{
+	struct mpc_link *link = mpc_get_link(ch);
+	struct mpc_flist *flist;
+
+	CHECK_LINK(link);
+
+	flist = calloc(1, sizeof(*flist));
+	if (!flist)
+		return -1;
+	flist->pd = pd;
+	flist->next = link->flist;
+	link->flist = flist;
+	return 0;
+}
+
+/* From: minipc-server.c -- but no log file */
+int minipc_unexport(struct minipc_ch *ch, const struct minipc_pd *pd)
+{
+	struct mpc_link *link = mpc_get_link(ch);
+	struct mpc_flist *flist;
+
+	CHECK_LINK(link);
+	/* We must find the flist that points to pd */
+	for (flist = link->flist; flist; flist = flist->next)
+		if (flist->pd == pd)
+			break;
+	if (!flist) {
+		errno = EINVAL;
+		return -1;
+	}
+	flist = container_of(&pd, struct mpc_flist, pd);
+	mpc_free_flist(link, flist);
+	return 0;
+}
+
+
+/* From: minipc-server.c */
+uint32_t *minipc_get_next_arg(uint32_t arg[], uint32_t atype)
+{
+	int asize;
+	char *s = (void *)arg;
+
+	if (MINIPC_GET_ATYPE(atype) != MINIPC_ATYPE_STRING)
+		asize = MINIPC_GET_ANUM(MINIPC_GET_ASIZE(atype));
+	else
+		asize = MINIPC_GET_ANUM(strlen(s) + 1);
+	return arg + asize;
+}
+
+/* From: minipc-server.c (mostly: mpc_handle_client) */
+int minipc_server_action(struct minipc_ch *ch, int timeoutms)
+{
+	struct mpc_link *link = mpc_get_link(ch);
+
+	struct mpc_req_packet *p_in;
+	struct mpc_rep_packet *p_out;
+	struct mpc_shmem *shm = link->memaddr;
+	const struct minipc_pd *pd;
+	struct mpc_flist *flist;
+	int i;
+
+	CHECK_LINK(link);
+
+	/* keep track of the request in an otherwise unused field */
+	if (shm->nrequest == link->pid)
+		return 0;
+	link->pid = shm->nrequest;
+
+	p_in = &shm->request;
+	p_out = &shm->reply;
+
+	/* use p_in->name to look for the function */
+	for (flist = link->flist; flist; flist = flist->next)
+		if (!(strcmp(p_in->name, flist->pd->name)))
+			break;
+	if (!flist) {
+		p_out->type = MINIPC_ARG_ENCODE(MINIPC_ATYPE_ERROR, int);
+		*(int *)(&p_out->val) = EOPNOTSUPP;
+		goto send_reply;
+	}
+	pd = flist->pd;
+
+	/* call the function and send back stuff */
+	i = pd->f(pd, p_in->args, p_out->val);
+	if (i < 0) {
+		p_out->type = MINIPC_ARG_ENCODE(MINIPC_ATYPE_ERROR, int);
+		*(int *)(&p_out->val) = errno;
+	} else {
+		/* Use retval, but fix the length for strings */
+		if (MINIPC_GET_ATYPE(pd->retval) == MINIPC_ATYPE_STRING) {
+			int size = strlen((char *)p_out->val) + 1;
+
+			size = (size + 3) & ~3; /* align */
+			p_out->type =
+				__MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, size);
+		} else {
+			p_out->type = pd->retval;
+		}
+	}
+
+ send_reply:
+	shm->nreply++; /* message already in place */
+	return 0;
+}