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Commit b452cfbf authored by Alessandro Rubini's avatar Alessandro Rubini
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userspace/include from svn 1116

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userspace/include/at91/at91_pio.h 0 → 100644
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/*
* arch/arm/mach-at91/include/mach/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif
userspace/include/at91/at91_pmc.h 0 → 100644
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/*
* arch/arm/mach-at91/include/mach/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock Enable [some SAM9 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif
userspace/include/at91/at91sam9263.h 0 → 100644
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/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif
userspace/include/at91/at91sam9_smc.h 0 → 100644
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/*
* arch/arm/mach-at91/include/mach/at91sam9_smc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* Static Memory Controllers (SMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#endif
#endif
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/**
* @file ad9516o.h
*
* @brief AD9516-O clock generator definitions
*
* The AD9516-O is controller through an SPI interface. This file
* provides definitions for the different addresses of the module
* to make its configuration easier to read.
*
* Copyright (c) 2009 CERN
* @author Emilio G. Cota <emilio.garcia.cota@cern.ch>
*
* @section license_sec License
* Released under the GPL v2. (and only v2, not any later version)
*/
#ifndef _AD9516O_H_
#define _AD9516O_H_
/*
* AD9516-O Adress Map
*/
#define AD9516_SERIALPORT 0x00
#define AD9516_READBACK 0x04
#define AD9516_PDF_CP 0x10
#define AD9516_RCOUNT_LSB 0x11
#define AD9516_RCOUNT_MSB 0x12
#define AD9516_ACOUNT 0x13
#define AD9516_BCOUNT_LSB 0x14
#define AD9516_BCOUNT_MSB 0x15
#define AD9516_PLL1 0x16
#define AD9516_PLL2 0x17
#define AD9516_PLL3 0x18
#define AD9516_PLL4 0x19
#define AD9516_PLL5 0x1A
#define AD9516_PLL6 0x1B
#define AD9516_PLL7 0x1C
#define AD9516_PLL8 0x1D
#define AD9516_PLL9 0x1E
#define AD9516_PLLREADBACK 0x1F
/* Fine Delay Adjust: OUT6 to OUT9 */
#define AD9516_OUT6DELAY_BP 0xA0
#define AD9516_OUT6DELAY_FS 0xA1
#define AD9516_OUT6DELAY_FR 0xA2
#define AD9516_OUT7DELAY_BP 0xA3
#define AD9516_OUT7DELAY_FS 0xA4
#define AD9516_OUT7DELAY_FR 0xA5
#define AD9516_OUT8DELAY_BP 0xA6
#define AD9516_OUT8DELAY_FS 0xA7
#define AD9516_OUT8DELAY_FR 0xA8
#define AD9516_OUT9DELAY_BP 0xA9
#define AD9516_OUT9DELAY_FS 0xAA
#define AD9516_OUT9DELAY_FR 0xAB
/* LVPECL Outputs */
#define AD9516_LVPECL_OUT0 0xF0
#define AD9516_LVPECL_OUT1 0xF1
#define AD9516_LVPECL_OUT2 0xF2
#define AD9516_LVPECL_OUT3 0xF3
#define AD9516_LVPECL_OUT4 0xF4
#define AD9516_LVPECL_OUT5 0xF5
/* LVDS/CMOS Outputs */
#define AD9516_LVCMOS_OUT6 0x140
#define AD9516_LVCMOS_OUT7 0x141
#define AD9516_LVCMOS_OUT8 0x142
#define AD9516_LVCMOS_OUT9 0x143
/* LVPECL Channel Dividers */
#define AD9516_PECLDIV0_1 0x190
#define AD9516_PECLDIV0_2 0x191
#define AD9516_PECLDIV0_3 0x192
#define AD9516_PECLDIV1_1 0x193
#define AD9516_PECLDIV1_2 0x194
#define AD9516_PECLDIV1_3 0x195
#define AD9516_PECLDIV2_1 0x196
#define AD9516_PECLDIV2_2 0x197
#define AD9516_PECLDIV2_3 0x198
/* LVDS/CMOS Channel Dividers */
#define AD9516_CMOSDIV3_1 0x199
#define AD9516_CMOSDIV3_PHO 0x19A
#define AD9516_CMOSDIV3_2 0x19B
#define AD9516_CMOSDIV3_BYPASS 0x19C
#define AD9516_CMOSDIV3_DCCOFF 0x19D
#define AD9516_CMOSDIV4_1 0x19E
#define AD9516_CMOSDIV4_PHO 0x19F
#define AD9516_CMOSDIV4_2 0x1A0
#define AD9516_CMOSDIV4_BYPASS 0x1A1
#define AD9516_CMOSDIV4_DCCOFF 0x1A2
/* VCO Divider and CLK Input */
#define AD9516_VCO_DIVIDER 0x1E0
#define AD9516_INPUT_CLKS 0x1E1
/* System */
#define AD9516_POWDOWN_SYNC 0x230
/* Update All Registers */
#define AD9516_UPDATE_ALL 0x232
int shw_ad9516_init();
int shw_use_external_reference(int enable);
#endif /* _AD9516O_H_ */
userspace/include/hw/clkb_io.h 0 → 100644
+ 23
− 0
View file @ b452cfbf
#ifndef __CLKB_H
#define __CLKB_H
#include <inttypes.h>
#define _CLKB_WB_BUS(x) ((x)<<8)
#define CLKB_BASE_REVID _CLKB_WB_BUS(0)
#define CLKB_BASE_HPLL _CLKB_WB_BUS(1)
#define CLKB_BASE_GPIO _CLKB_WB_BUS(2)
#define CLKB_BASE_DMPLL _CLKB_WB_BUS(3)
#define CLKB_BASE_CALIBRATOR _CLKB_WB_BUS(4)
#define CLKB_REG_IDCODE 0
int shw_clkb_init();
int shw_clkb_init_cmi();
//void shw_clkb_dac_write(int dac, int val);
#endif
userspace/include/hw/dmpll.h 0 → 100644
+ 29
− 0
View file @ b452cfbf
/* FIXME: rewrite this _properly_ */
#ifndef __DMPLL_H
#define __DMPLL_H
#include <hw/dmpll_regs.h>
#define DMPLL_CHANNEL_EXT_REF 2
#define DMPLL_CHANNEL_UP0 0
#define DMPLL_CHANNEL_UP1 1
int shw_dmpll_init();
int shw_dmpll_check_lock();
int shw_dmpll_lock(const char *source);
int shw_dmpll_phase_shift(const char *source, int phase_shift);
int shw_dmpll_shifter_busy(const char *source);
typedef struct {
int deglitch_threshold;
double f_n;
double eta;
int ki;
int kp;
int channel;
double phase_setpoint[4];
} dmpll_params_t;
#endif
userspace/include/hw/dmpll_regs.h 0 → 100644
+ 337
− 0
View file @ b452cfbf
/*
Register definitions for slave core: DMTD phase-shifting PLL
* File : ../../../software/include/hw/dmpll_regs.h
* Author : auto-generated by wbgen2 from dmpll_wb.wb
* Created : Fri Jul 23 20:52:22 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dmpll_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMPLL_WB_WB
#define __WBGEN2_REGDEFS_DMPLL_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: DMPLL Control Register */
/* definitions for field: DMPLL Enable in reg: DMPLL Control Register */
#define DMPLL_PCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMPLL Force Freq mode in reg: DMPLL Control Register */
#define DMPLL_PCR_FORCE_F WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC serial clock select in reg: DMPLL Control Register */
#define DMPLL_PCR_DAC_CLKSEL_MASK WBGEN2_GEN_MASK(4, 3)
#define DMPLL_PCR_DAC_CLKSEL_SHIFT 4
#define DMPLL_PCR_DAC_CLKSEL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define DMPLL_PCR_DAC_CLKSEL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Reference clock input select in reg: DMPLL Control Register */
#define DMPLL_PCR_REFSEL_MASK WBGEN2_GEN_MASK(8, 2)
#define DMPLL_PCR_REFSEL_SHIFT 8
#define DMPLL_PCR_REFSEL_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define DMPLL_PCR_REFSEL_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Phase shifter speed in reg: DMPLL Control Register */
#define DMPLL_PCR_PS_SPEED_MASK WBGEN2_GEN_MASK(10, 12)
#define DMPLL_PCR_PS_SPEED_SHIFT 10
#define DMPLL_PCR_PS_SPEED_W(value) WBGEN2_GEN_WRITE(value, 10, 12)
#define DMPLL_PCR_PS_SPEED_R(reg) WBGEN2_GEN_READ(reg, 10, 12)
/* definitions for field: PLL Reset in reg: DMPLL Control Register */
#define DMPLL_PCR_SWRST WBGEN2_GEN_MASK(31, 1)
/* definitions for register: DMPLL Frequency Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: DMPLL Frequency Branch Gain Register */
#define DMPLL_FBGR_F_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define DMPLL_FBGR_F_KP_SHIFT 0
#define DMPLL_FBGR_F_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_FBGR_F_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: DMPLL Frequency Branch Gain Register */
#define DMPLL_FBGR_F_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define DMPLL_FBGR_F_KI_SHIFT 16
#define DMPLL_FBGR_F_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define DMPLL_FBGR_F_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: DMPLL Phase Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: DMPLL Phase Branch Gain Register */
#define DMPLL_PBGR_P_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define DMPLL_PBGR_P_KP_SHIFT 0
#define DMPLL_PBGR_P_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_PBGR_P_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: DMPLL Phase Branch Gain Register */
#define DMPLL_PBGR_P_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define DMPLL_PBGR_P_KI_SHIFT 16
#define DMPLL_PBGR_P_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define DMPLL_PBGR_P_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: DMPLL Lock Detect Control Register */
/* definitions for field: Lock detect threshold in reg: DMPLL Lock Detect Control Register */
#define DMPLL_LDCR_LD_THR_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_LDCR_LD_THR_SHIFT 0
#define DMPLL_LDCR_LD_THR_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_LDCR_LD_THR_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Lock detect samples in reg: DMPLL Lock Detect Control Register */
#define DMPLL_LDCR_LD_SAMP_MASK WBGEN2_GEN_MASK(16, 12)
#define DMPLL_LDCR_LD_SAMP_SHIFT 16
#define DMPLL_LDCR_LD_SAMP_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DMPLL_LDCR_LD_SAMP_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMPLL Status Register */
/* definitions for field: Frequency lock in reg: DMPLL Status Register */
#define DMPLL_PSR_FREQ_LK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Phase lock in reg: DMPLL Status Register */
#define DMPLL_PSR_PHASE_LK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Loss-of-lock indicator in reg: DMPLL Status Register */
#define DMPLL_PSR_LOCK_LOST WBGEN2_GEN_MASK(2, 1)
/* definitions for register: DMPLL Deglitcher Control Register for Reference input 0 clock */
/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_LO_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN0_THR_LO_SHIFT 0
#define DMPLL_DGCR_IN0_THR_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN0_THR_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_HI_MASK WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN0_THR_HI_SHIFT 12
#define DMPLL_DGCR_IN0_THR_HI_W(value) WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN0_THR_HI_R(reg) WBGEN2_GEN_READ(reg, 12, 12)
/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_GLITCH_MASK WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN0_THR_GLITCH_SHIFT 24
#define DMPLL_DGCR_IN0_THR_GLITCH_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN0_THR_GLITCH_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: DMPLL Deglitcher Control Register for Reference input 1 clock */
/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_LO_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN1_THR_LO_SHIFT 0
#define DMPLL_DGCR_IN1_THR_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN1_THR_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_HI_MASK WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN1_THR_HI_SHIFT 12
#define DMPLL_DGCR_IN1_THR_HI_W(value) WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN1_THR_HI_R(reg) WBGEN2_GEN_READ(reg, 12, 12)
/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_GLITCH_MASK WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN1_THR_GLITCH_SHIFT 24
#define DMPLL_DGCR_IN1_THR_GLITCH_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN1_THR_GLITCH_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: DMPLL Deglitcher Control Register for Reference input 2 clock */
/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_LO_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN2_THR_LO_SHIFT 0
#define DMPLL_DGCR_IN2_THR_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN2_THR_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_HI_MASK WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN2_THR_HI_SHIFT 12
#define DMPLL_DGCR_IN2_THR_HI_W(value) WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN2_THR_HI_R(reg) WBGEN2_GEN_READ(reg, 12, 12)
/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_GLITCH_MASK WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN2_THR_GLITCH_SHIFT 24
#define DMPLL_DGCR_IN2_THR_GLITCH_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN2_THR_GLITCH_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: DMPLL Deglitcher Control Register for Reference input 3 clock */
/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_LO_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN3_THR_LO_SHIFT 0
#define DMPLL_DGCR_IN3_THR_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN3_THR_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_HI_MASK WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN3_THR_HI_SHIFT 12
#define DMPLL_DGCR_IN3_THR_HI_W(value) WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN3_THR_HI_R(reg) WBGEN2_GEN_READ(reg, 12, 12)
/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_GLITCH_MASK WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN3_THR_GLITCH_SHIFT 24
#define DMPLL_DGCR_IN3_THR_GLITCH_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN3_THR_GLITCH_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: DMPLL Deglitcher Control Register for TCXO clock clock */
/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_LO_MASK WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_FB_THR_LO_SHIFT 0
#define DMPLL_DGCR_FB_THR_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_FB_THR_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_HI_MASK WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_FB_THR_HI_SHIFT 12
#define DMPLL_DGCR_FB_THR_HI_W(value) WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_FB_THR_HI_R(reg) WBGEN2_GEN_READ(reg, 12, 12)
/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_GLITCH_MASK WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_FB_THR_GLITCH_SHIFT 24
#define DMPLL_DGCR_FB_THR_GLITCH_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_FB_THR_GLITCH_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 0 clock */
/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_PSCR_IN0_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN0_PS_VAL_SHIFT 0
#define DMPLL_PSCR_IN0_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN0_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_PSCR_IN0_BUSY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 1 clock */
/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_PSCR_IN1_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN1_PS_VAL_SHIFT 0
#define DMPLL_PSCR_IN1_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN1_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_PSCR_IN1_BUSY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 2 clock */
/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_PSCR_IN2_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN2_PS_VAL_SHIFT 0
#define DMPLL_PSCR_IN2_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN2_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_PSCR_IN2_BUSY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 3 clock */
/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_PSCR_IN3_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN3_PS_VAL_SHIFT 0
#define DMPLL_PSCR_IN3_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN3_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_PSCR_IN3_BUSY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */
/* definitions for field: Freq/phase error in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */
#define DMPLL_RFIFO_R0_ERR_VAL_MASK WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R0_ERR_VAL_SHIFT 0
#define DMPLL_RFIFO_R0_ERR_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R0_ERR_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 18)
/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */
/* definitions for field: Ref tag in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */
#define DMPLL_RFIFO_R1_TAG_REF_MASK WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R1_TAG_REF_SHIFT 0
#define DMPLL_RFIFO_R1_TAG_REF_W(value) WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R1_TAG_REF_R(reg) WBGEN2_GEN_READ(reg, 0, 18)
/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
/* definitions for field: Feedback tag in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_RFIFO_R2_TAG_FB_MASK WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R2_TAG_FB_SHIFT 0
#define DMPLL_RFIFO_R2_TAG_FB_W(value) WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R2_TAG_FB_R(reg) WBGEN2_GEN_READ(reg, 0, 18)
/* definitions for field: Freq/phase mode in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_RFIFO_R2_FP_MODE WBGEN2_GEN_MASK(29, 1)
/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */
/* definitions for field: DAC output in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */
#define DMPLL_RFIFO_R3_DAC_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define DMPLL_RFIFO_R3_DAC_VAL_SHIFT 0
#define DMPLL_RFIFO_R3_DAC_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_RFIFO_R3_DAC_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'DMPLL Phase/Output record FIFO' control/status register */
#define DMPLL_RFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG DMPLL Control Register */
#define DMPLL_REG_PCR 0x00000000
/* [0x4]: REG DMPLL Frequency Branch Gain Register */
#define DMPLL_REG_FBGR 0x00000004
/* [0x8]: REG DMPLL Phase Branch Gain Register */
#define DMPLL_REG_PBGR 0x00000008
/* [0xc]: REG DMPLL Lock Detect Control Register */
#define DMPLL_REG_LDCR 0x0000000c
/* [0x10]: REG DMPLL Status Register */
#define DMPLL_REG_PSR 0x00000010
/* [0x14]: REG DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_REG_DGCR_IN0 0x00000014
/* [0x18]: REG DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_REG_DGCR_IN1 0x00000018
/* [0x1c]: REG DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_REG_DGCR_IN2 0x0000001c
/* [0x20]: REG DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_REG_DGCR_IN3 0x00000020
/* [0x24]: REG DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_REG_DGCR_FB 0x00000024
/* [0x28]: REG DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_REG_PSCR_IN0 0x00000028
/* [0x2c]: REG DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_REG_PSCR_IN1 0x0000002c
/* [0x30]: REG DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_REG_PSCR_IN2 0x00000030
/* [0x34]: REG DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_REG_PSCR_IN3 0x00000034
/* [0x38]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */
#define DMPLL_REG_RFIFO_R0 0x00000038
/* [0x3c]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */
#define DMPLL_REG_RFIFO_R1 0x0000003c
/* [0x40]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_REG_RFIFO_R2 0x00000040
/* [0x44]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */
#define DMPLL_REG_RFIFO_R3 0x00000044
/* [0x48]: REG FIFO 'DMPLL Phase/Output record FIFO' control/status register */
#define DMPLL_REG_RFIFO_CSR 0x00000048
#endif
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/*
Register definitions for slave core: DMTD PHY Calibrator
* File : ../../../software/include/hw/dmtd_calibrator_regs.h
* Author : auto-generated by wbgen2 from wrsw_calibrator_dmtd.wb
* Created : Mon Aug 23 14:38:14 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_calibrator_dmtd.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
#define __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable in reg: Control Register */
#define DPC_CR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Compare clock select in reg: Control Register */
#define DPC_CR_IN_SEL_MASK WBGEN2_GEN_MASK(8, 4)
#define DPC_CR_IN_SEL_SHIFT 8
#define DPC_CR_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DPC_CR_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: DMTD averaging samples in reg: Control Register */
#define DPC_CR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define DPC_CR_N_AVG_SHIFT 16
#define DPC_CR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DPC_CR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Status register */
/* definitions for field: Phase shift value in reg: Status register */
#define DPC_SR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DPC_SR_PS_VAL_SHIFT 0
#define DPC_SR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DPC_SR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase shift value ready in reg: Status register */
#define DPC_SR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* [0x0]: REG Control Register */
#define DPC_REG_CR 0x00000000
/* [0x4]: REG Status register */
#define DPC_REG_SR 0x00000004
#endif
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userspace/include/hw/endpoint_regs.h 0 → 100644
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/*
Register definitions for slave core: WR switch endpoint controller
* File : ../../../software/include/hw/endpoint_regs.h
* Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
* Created : Sun Apr 10 01:27:43 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Endpoint Control Register */
/* definitions for field: Port identifier in reg: Endpoint Control Register */
#define EP_ECR_PORTID_MASK WBGEN2_GEN_MASK(0, 5)
#define EP_ECR_PORTID_SHIFT 0
#define EP_ECR_PORTID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define EP_ECR_PORTID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_TXTS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Receive timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_RXTS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamping counter synchronization start in reg: Timestamping Control Register */
#define EP_TSCR_CS_START WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timestamping counter synchronization done in reg: Timestamping Control Register */
#define EP_TSCR_CS_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
#define EP_RFCR_A_RUNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX accept giants in reg: RX Deframer Control Register */
#define EP_RFCR_A_GIANT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
#define EP_FCR_TX_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define EP_FCR_TX_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: TX pause quanta in reg: Flow Control Register */
#define EP_FCR_TX_QUANTA_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_FCR_TX_QUANTA_SHIFT 16
#define EP_FCR_TX_QUANTA_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_FCR_TX_QUANTA_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Endpoint MAC address high part register */
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
#define EP_MDIO_CR_DATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_CR_DATA_SHIFT 0
#define EP_MDIO_CR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_CR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Register Address in reg: MDIO Control Register */
#define EP_MDIO_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_CR_ADDR_SHIFT 16
#define EP_MDIO_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
/* definitions for register: Debug/Status register */
/* definitions for field: Link status in reg: Debug/Status register */
#define EP_DSR_LSTATUS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Address Filter Control Register */
/* definitions for field: Filtering Enable in reg: Address Filter Control Register */
#define EP_AFCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Filtering rule index in reg: Address Filter Control Register */
#define EP_AFCR_RULE_SEL_MASK WBGEN2_GEN_MASK(1, 3)
#define EP_AFCR_RULE_SEL_SHIFT 1
#define EP_AFCR_RULE_SEL_W(value) WBGEN2_GEN_WRITE(value, 1, 3)
#define EP_AFCR_RULE_SEL_R(reg) WBGEN2_GEN_READ(reg, 1, 3)
/* definitions for field: Filtering Matrix Write Address in reg: Address Filter Control Register */
#define EP_AFCR_MATRIX_ADDR_MASK WBGEN2_GEN_MASK(4, 8)
#define EP_AFCR_MATRIX_ADDR_SHIFT 4
#define EP_AFCR_MATRIX_ADDR_W(value) WBGEN2_GEN_WRITE(value, 4, 8)
#define EP_AFCR_MATRIX_ADDR_R(reg) WBGEN2_GEN_READ(reg, 4, 8)
/* definitions for field: Filtering Matrix Write Data in reg: Address Filter Control Register */
#define EP_AFCR_MATRIX_DATA_MASK WBGEN2_GEN_MASK(12, 8)
#define EP_AFCR_MATRIX_DATA_SHIFT 12
#define EP_AFCR_MATRIX_DATA_W(value) WBGEN2_GEN_WRITE(value, 12, 8)
#define EP_AFCR_MATRIX_DATA_R(reg) WBGEN2_GEN_READ(reg, 12, 8)
/* definitions for field: Filtering Matrix Write Strobe in reg: Address Filter Control Register */
#define EP_AFCR_MATRIX_WRITE_P WBGEN2_GEN_MASK(20, 1)
/* definitions for register: Address Filter Register 0 */
/* definitions for field: Destination MAC Matching Enable in reg: Address Filter Register 0 */
#define EP_AFR0_DMAC_EN_MASK WBGEN2_GEN_MASK(0, 1)
#define EP_AFR0_DMAC_EN_SHIFT 0
#define EP_AFR0_DMAC_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define EP_AFR0_DMAC_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: VLAN Matching Enable in reg: Address Filter Register 0 */
#define EP_AFR0_VID_EN_MASK WBGEN2_GEN_MASK(1, 1)
#define EP_AFR0_VID_EN_SHIFT 1
#define EP_AFR0_VID_EN_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define EP_AFR0_VID_EN_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Ethertype Matching Enable in reg: Address Filter Register 0 */
#define EP_AFR0_ETYPE_EN_MASK WBGEN2_GEN_MASK(2, 1)
#define EP_AFR0_ETYPE_EN_SHIFT 2
#define EP_AFR0_ETYPE_EN_W(value) WBGEN2_GEN_WRITE(value, 2, 1)
#define EP_AFR0_ETYPE_EN_R(reg) WBGEN2_GEN_READ(reg, 2, 1)
/* definitions for field: VID Compare Value in reg: Address Filter Register 0 */
#define EP_AFR0_VID_MASK WBGEN2_GEN_MASK(3, 12)
#define EP_AFR0_VID_SHIFT 3
#define EP_AFR0_VID_W(value) WBGEN2_GEN_WRITE(value, 3, 12)
#define EP_AFR0_VID_R(reg) WBGEN2_GEN_READ(reg, 3, 12)
/* definitions for register: Address Filter Register 1 */
/* definitions for field: Destination MAC[31:0] compare value in reg: Address Filter Register 1 */
#define EP_AFR1_DMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define EP_AFR1_DMAC_LO_SHIFT 0
#define EP_AFR1_DMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define EP_AFR1_DMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Address Filter Register 2 */
/* definitions for field: Destination MAC [47:32] compare value in reg: Address Filter Register 2 */
#define EP_AFR2_DMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_AFR2_DMAC_HI_SHIFT 0
#define EP_AFR2_DMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_AFR2_DMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Ethertype compare value in reg: Address Filter Register 2 */
#define EP_AFR2_ETYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_AFR2_ETYPE_SHIFT 16
#define EP_AFR2_ETYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_AFR2_ETYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG Endpoint Control Register */
#define EP_REG_ECR 0x00000000
/* [0x4]: REG Timestamping Control Register */
#define EP_REG_TSCR 0x00000004
/* [0x8]: REG RX Deframer Control Register */
#define EP_REG_RFCR 0x00000008
/* [0xc]: REG Flow Control Register */
#define EP_REG_FCR 0x0000000c
/* [0x10]: REG Endpoint MAC address high part register */
#define EP_REG_MACH 0x00000010
/* [0x14]: REG Endpoint MAC address low part register */
#define EP_REG_MACL 0x00000014
/* [0x18]: REG DMTD Control Register */
#define EP_REG_DMCR 0x00000018
/* [0x1c]: REG DMTD Status register */
#define EP_REG_DMSR 0x0000001c
/* [0x20]: REG MDIO Control Register */
#define EP_REG_MDIO_CR 0x00000020
/* [0x24]: REG MDIO Status Register */
#define EP_REG_MDIO_SR 0x00000024
/* [0x28]: REG Identification register */
#define EP_REG_IDCODE 0x00000028
/* [0x2c]: REG Debug/Status register */
#define EP_REG_DSR 0x0000002c
/* [0x30]: REG Address Filter Control Register */
#define EP_REG_AFCR 0x00000030
/* [0x34]: REG Address Filter Register 0 */
#define EP_REG_AFR0 0x00000034
/* [0x38]: REG Address Filter Register 1 */
#define EP_REG_AFR1 0x00000038
/* [0x3c]: REG Address Filter Register 2 */
#define EP_REG_AFR2 0x0000003c
#endif
userspace/include/hw/fpga_regs.h 0 → 100644
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#ifndef __FPGA_IO_H
#define __FPGA_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include "pio.h"
#define FPGA_BASE_ADDR _fpga_base_virt
extern volatile uint8_t *_fpga_base_virt;
#define _fpga_writel(reg, val){ *(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)) = (val); }
#define _fpga_readl(reg) (*(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)))
#define _FPGA_BUS_2_ADDR(x) ((x) * 0x10000)
#define FPGA_BASE_REVID _FPGA_BUS_2_ADDR(0)
#define FPGA_BASE_GPIO _FPGA_BUS_2_ADDR(1)
#define FPGA_BASE_SPIM _FPGA_BUS_2_ADDR(2)
#define FPGA_BASE_VIC _FPGA_BUS_2_ADDR(3)
#define FPGA_BASE_EP_UP0 _FPGA_BUS_2_ADDR(4)
#define FPGA_BASE_EP_UP1 _FPGA_BUS_2_ADDR(5)
#define FPGA_BASE_EP_DP0 _FPGA_BUS_2_ADDR(6)
#define FPGA_BASE_EP_DP1 _FPGA_BUS_2_ADDR(7)
#define FPGA_BASE_EP_DP2 _FPGA_BUS_2_ADDR(8)
#define FPGA_BASE_EP_DP3 _FPGA_BUS_2_ADDR(9)
#define FPGA_BASE_EP_DP4 _FPGA_BUS_2_ADDR(10)
#define FPGA_BASE_EP_DP5 _FPGA_BUS_2_ADDR(11)
#define FPGA_BASE_EP_DP6 _FPGA_BUS_2_ADDR(12)
#define FPGA_BASE_EP_DP7 _FPGA_BUS_2_ADDR(13)
#define FPGA_BASE_PPS_GEN _FPGA_BUS_2_ADDR(14)
#define FPGA_BASE_CALIBRATOR _FPGA_BUS_2_ADDR(15)
#define FPGA_BASE_RTU _FPGA_BUS_2_ADDR(16)
#define FPGA_BASE_RTU_TESTUNIT _FPGA_BUS_2_ADDR(17)
#define GPIO_REG_CODR 0x0
#define GPIO_REG_SODR 0x4
#define GPIO_REG_DDR 0x8
#define GPIO_REG_PSR 0xc
#define SPI_REG_SPITX 0x4
#define SPI_REG_SPIRX 0x8
#define SPI_REG_SPICTL 0x0
#define SPICTL_ENABLE(x) ((x)?(1<<2):0)
#define SPICTL_CSEN(x) ((x)?(1<<0):0)
#define SPICTL_CSDIS(x) ((x)?(1<<1):0)
#define SPICTL_BUSY(rval) ((rval)&(1<<3)?1:0)
#define SPICTL_CLKDIV(value) (((value)&0xff) << 8)
#define GPIO_PIN_LED0_A 0
#define GPIO_PIN_LED0_K 1
#define GPIO_PIN_LED1_A 2
#define GPIO_PIN_LED1_K 3
#define GPIO_PIN_LED2_A 4
#define GPIO_PIN_LED2_K 5
#define GPIO_PIN_LED3_A 6
#define GPIO_PIN_LED3_K 7
#define GPIO_PIN_CLKB_RST 31
#define GPIO_PIN_UP0_SFP_SDA 8
#define GPIO_PIN_UP0_SFP_SCL 9
#define GPIO_PIN_UP0_SFP_LOS 10
#define GPIO_PIN_UP0_SFP_TX_FAULT 11
#define GPIO_PIN_UP0_SFP_TX_DISABLE 12
#define GPIO_PIN_UP0_SFP_DETECT 13
#define GPIO_PIN_UP0_PRBSEN 14
#define GPIO_PIN_UP0_SYNCEN 15
#define GPIO_PIN_UP0_LOOPEN 16
#define GPIO_PIN_UP0_ENABLE 17
#define GPIO_PIN_UP1_SFP_SDA 18
#define GPIO_PIN_UP1_SFP_SCL 19
#define GPIO_PIN_UP1_SFP_LOS 20
#define GPIO_PIN_UP1_SFP_TX_FAULT 21
#define GPIO_PIN_UP1_SFP_TX_DISABLE 22
#define GPIO_PIN_UP1_SFP_DETECT 23
#define GPIO_PIN_UP1_PRBSEN 24
#define GPIO_PIN_UP1_SYNCEN 25
#define GPIO_PIN_UP1_LOOPEN 26
#define GPIO_PIN_UP1_ENABLE 27
// GigaSpy wishbone registers
#define GIGASPY_MEM_SIZE 8192
#define GSPY_REG_GSCTL 0x0
#define GSPY_REG_GSTRIGCTL 0x4
#define GSPY_REG_GSSTAT 0x8
#define GSPY_REG_GSNSAMPLES 0xc
#define GSPY_REG_GSTRIGADDR 0x10
#define GSPY_REG_GSTESTCTL 0x14
#define GSPY_REG_GSTESTCNT 0x18
#define GSPY_REG_GSCLKFREQ 0x1c
#define GSPY_MEM_CH0 0x8000
#define GSPY_MEM_CH1 0x10000
#define GSPY_GSCTL_CH0_ENABLE(x) ((x)?(1<<0):(0))
#define GSPY_GSCTL_CH1_ENABLE(x) ((x)?(1<<1):(0))
#define GSPY_GSCTL_SLAVE0_ENABLE(x) ((x)?(1<<2):(0))
#define GSPY_GSCTL_SLAVE1_ENABLE(x) ((x)?(1<<3):(0))
#define GSPY_GSCTL_LOAD_TRIG0(x) ((x)?(1<<4):(0))
#define GSPY_GSCTL_LOAD_TRIG1(x) ((x)?(1<<5):(0))
#define GSPY_GSCTL_RESET_TRIG0(x) ((x)?(1<<6):(0))
#define GSPY_GSCTL_RESET_TRIG1(x) ((x)?(1<<7):(0))
#define GSPY_GSTRIGCTL_TRIG0_VAL(k,v) (((k)?(1<<8):0) | ((v) & 0xff))
#define GSPY_GSTRIGCTL_TRIG1_VAL(k,v) (((k)?(1<<24):0) | (((v) & 0xff)<<16))
#define GSPY_GSTRIGCTL_TRIG0_EN(x) (((x)?(1<<15):0))
#define GSPY_GSTRIGCTL_TRIG1_EN(x) (((x)?(1<<31):0))
#define GSPY_GSNSAMPLES(x) ((x)&0x1fff)
#define GSPY_GSSTAT_TRIG_DONE0(reg) ((reg)&(1<<0)?1:0)
#define GSPY_GSSTAT_TRIG_DONE1(reg) ((reg)&(1<<1)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE0(reg) ((reg)&(1<<2)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE1(reg) ((reg)&(1<<3)?1:0)
#define GSPY_GSTRIGADDR_CH0(reg) ((reg)&0x1fff)
#define GSPY_GSTRIGADDR_CH1(reg) (((reg)>>16)&0x1fff)
#define GSPY_GSTESTCTL_ENABLE 0x1
#define GSPY_GSTESTCTL_RST_CNTR 0x2
#define GSPY_GSTESTCTL_CONNECT 0x4
#define GSPY_GSTESTCTL_PHYIO_ENABLE 0x100
#define GSPY_GSTESTCTL_PHYIO_SYNCEN 0x200
#define GSPY_GSTESTCTL_PHYIO_LOOPEN 0x400
#define GSPY_GSTESTCTL_PHYIO_PRBSEN 0x800
#endif
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#ifndef __FPGABOOT_H
#define __FPGABOOT_H
#include <inttypes.h>
#define FPGA_ID_MAIN 0
#define FPGA_ID_CLKB 1
#define DEFAULT_FPGA_IMAGE "/fpga/fpga.img"
#define REVISION_ANY -1
static const char FPGA_IMAGE_MAGIC[4] = { 'w','r','f','i' };
struct fpga_image_header {
char magic[4];
uint32_t num_fpgas;
};
struct fpga_image_entry {
char *fpga_name; // name of the FPGA (for example: MAIN, CLKB)
char *fw_name; // name of the firmware (for example: board_test, rtu_test).
uint32_t hash_reg; // MD5 hash of the firmware ID.
uint32_t revision;
uint32_t size;
uint32_t compressed_size;
uint8_t *image_buf;
};
int mblaster_init();
int shw_fpgaboot_init();
int shw_load_fpga_bitstream(int fpga_id, uint8_t *bitstream, uint32_t bitstream_size);
int shw_request_fpga_firmware(int fpga_id, const char *firmware_name);
int shw_boot_fpga(int fpga_id);
int shw_set_fpga_firmware_path(const char *path);
#endif
userspace/include/hw/gigaspy_regs.h 0 → 100644
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#ifndef __GIGASPY_REGS_H
#define __GIGASPY_REGS_H
// GigaSpy wishbone registers
#define GSPY_REG_GSCTL 0x0
#define GSPY_REG_GSTRIGCTL 0x4
#define GSPY_REG_GSSTAT 0x8
#define GSPY_REG_GSNSAMPLES 0xc
#define GSPY_REG_GSTRIGADDR 0x10
#define GSPY_REG_GSTESTCTL 0x14
#define GSPY_REG_GSTESTCNT 0x18
#define GSPY_REG_GSCLKFREQ 0x1c
#define GSPY_GSCTL_CH0_ENABLE(x) ((x)?(1<<0):(0))
#define GSPY_GSCTL_CH1_ENABLE(x) ((x)?(1<<1):(0))
#define GSPY_GSCTL_SLAVE0_ENABLE(x) ((x)?(1<<2):(0))
#define GSPY_GSCTL_SLAVE1_ENABLE(x) ((x)?(1<<3):(0))
#define GSPY_GSCTL_LOAD_TRIG0(x) ((x)?(1<<4):(0))
#define GSPY_GSCTL_LOAD_TRIG1(x) ((x)?(1<<5):(0))
#define GSPY_GSCTL_RESET_TRIG0(x) ((x)?(1<<6):(0))
#define GSPY_GSCTL_RESET_TRIG1(x) ((x)?(1<<7):(0))
#define GSPY_GSTRIGCTL_TRIG0_VAL(k,v) (((k)?(1<<8):0) | ((v) & 0xff))
#define GSPY_GSTRIGCTL_TRIG1_VAL(k,v) (((k)?(1<<24):0) | (((v) & 0xff)<<16))
#define GSPY_GSTRIGCTL_TRIG0_EN(x) (((x)?(1<<15):0))
#define GSPY_GSTRIGCTL_TRIG1_EN(x) (((x)?(1<<31):0))
#define GSPY_GSNSAMPLES(x) ((x)&0x1fff)
#define GSPY_GSSTAT_TRIG_DONE0(reg) ((reg)&(1<<0)?1:0)
#define GSPY_GSSTAT_TRIG_DONE1(reg) ((reg)&(1<<1)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE0(reg) ((reg)&(1<<2)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE1(reg) ((reg)&(1<<3)?1:0)
#define GSPY_GSTRIGADDR_CH0(reg) ((reg)&0x1fff)
#define GSPY_GSTRIGADDR_CH1(reg) (((reg)>>16)&0x1fff)
#define GSPY_GSTESTCTL_ENABLE 0x1
#define GSPY_GSTESTCTL_RST_CNTR 0x2
#define GSPY_GSTESTCTL_CONNECT 0x4
#define GSPY_GSTESTCTL_PHYIO_ENABLE 0x100
#define GSPY_GSTESTCTL_PHYIO_SYNCEN 0x200
#define GSPY_GSTESTCTL_PHYIO_LOOPEN 0x400
#define GSPY_GSTESTCTL_PHYIO_PRBSEN 0x800
#endif
userspace/include/hw/hpll.h 0 → 100644
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// definitions for DMTD helper PLL
#ifndef __HPLL_H
#define __HPLL_H
#include <inttypes.h>
#include <hw/hpll_regs.h>
// Phase detector gating:
#define HPLL_PD_GATE_512 0
#define HPLL_PD_GATE_1K 1
#define HPLL_PD_GATE_2K 2
#define HPLL_PD_GATE_4K 3
#define HPLL_PD_GATE_8K 4
#define HPLL_PD_GATE_16K 5
#define HPLL_PD_GATE_32K 6
#define HPLL_PD_GATE_64K 7
// Frequency detector gating:
#define HPLL_FD_GATE_16K 0
#define HPLL_FD_GATE_32K 1
#define HPLL_FD_GATE_64K 2
#define HPLL_FD_GATE_128K 3
#define HPLL_FD_GATE_256K 4
#define HPLL_FD_GATE_512K 5
#define HPLL_FD_GATE_1M 6
#define HPLL_FD_GATE_2M 7
#define HPLL_REFSEL_UP0_RBCLK 2
#define HPLL_REFSEL_UP1_RBCLK 1
#define HPLL_REFSEL_LOCAL 0
typedef struct {
float ki_freq, kp_freq; // Kp/Ki for the frequency branch
float ki_phase, kp_phase; // Phase gain (target)
int phase_gain_steps; // number of phase gain (start to end) transition steps
uint64_t phase_gain_step_delay; // step delay for phase gain adjustment (in microseconds)
int N, delta; // divider settings: output_freq = input_freq * (N / (N+delta))
int freq_gating; // frequency detector gating
int phase_gating; // phase detector gating
int ref_sel; // reference clock select
int force_freqmode; // force frequency lock mode
double ki_phase_cur, kp_phase_cur; // Phase gain (current)
} hpll_params_t;
int shw_hpll_init();
//void shw_hpll_update();
int shw_hpll_check_lock();
//void shw_hpll_set_reference(int ref_clk);
void shw_hpll_reset();
void shw_hpll_load_regs(const hpll_params_t *params);
int shw_hpll_switch_reference(const char *if_name);
int shw_hpll_get_divider();
//void shw_hpll_start_recording(uint32_t *buffer, int params);
#endif
userspace/include/hw/hpll_regs.h 0 → 100644
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/*
Register definitions for slave core: DMTD Helper PLL
* File : ../../../software/include/hw/hpll_regs.h
* Author : auto-generated by wbgen2 from hpll_wb.wb
* Created : Mon Jun 21 14:16:43 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE hpll_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_HPLL_WB_WB
#define __WBGEN2_REGDEFS_HPLL_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: HPLL Control Register */
/* definitions for field: PLL Enable in reg: HPLL Control Register */
#define HPLL_PCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL Force Freq mode in reg: HPLL Control Register */
#define HPLL_PCR_FORCE_F WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC serial clock select in reg: HPLL Control Register */
#define HPLL_PCR_DAC_CLKSEL_MASK WBGEN2_GEN_MASK(4, 3)
#define HPLL_PCR_DAC_CLKSEL_SHIFT 4
#define HPLL_PCR_DAC_CLKSEL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define HPLL_PCR_DAC_CLKSEL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Phase detector gating period in reg: HPLL Control Register */
#define HPLL_PCR_PD_GATE_MASK WBGEN2_GEN_MASK(8, 3)
#define HPLL_PCR_PD_GATE_SHIFT 8
#define HPLL_PCR_PD_GATE_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define HPLL_PCR_PD_GATE_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Reference clock input select in reg: HPLL Control Register */
#define HPLL_PCR_REFSEL_MASK WBGEN2_GEN_MASK(11, 2)
#define HPLL_PCR_REFSEL_SHIFT 11
#define HPLL_PCR_REFSEL_W(value) WBGEN2_GEN_WRITE(value, 11, 2)
#define HPLL_PCR_REFSEL_R(reg) WBGEN2_GEN_READ(reg, 11, 2)
/* definitions for field: PLL Reset in reg: HPLL Control Register */
#define HPLL_PCR_SWRST WBGEN2_GEN_MASK(31, 1)
/* definitions for register: HPLL Divider Register */
/* definitions for field: Reference divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_REF_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_DIVR_DIV_REF_SHIFT 0
#define HPLL_DIVR_DIV_REF_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_DIVR_DIV_REF_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Feedback divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_FB_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_DIVR_DIV_FB_SHIFT 16
#define HPLL_DIVR_DIV_FB_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_DIVR_DIV_FB_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Frequency Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_FBGR_F_KP_SHIFT 0
#define HPLL_FBGR_F_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_FBGR_F_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_FBGR_F_KI_SHIFT 16
#define HPLL_FBGR_F_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_FBGR_F_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Phase Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_PBGR_P_KP_SHIFT 0
#define HPLL_PBGR_P_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_PBGR_P_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_PBGR_P_KI_SHIFT 16
#define HPLL_PBGR_P_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_PBGR_P_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Lock Detect Control Register */
/* definitions for field: Phase Lock detect threshold in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_THR_MASK WBGEN2_GEN_MASK(0, 8)
#define HPLL_LDCR_LD_THR_SHIFT 0
#define HPLL_LDCR_LD_THR_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define HPLL_LDCR_LD_THR_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Lock detect samples in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_SAMP_MASK WBGEN2_GEN_MASK(8, 8)
#define HPLL_LDCR_LD_SAMP_SHIFT 8
#define HPLL_LDCR_LD_SAMP_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define HPLL_LDCR_LD_SAMP_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: HPLL Frequency branch control register */
/* definitions for field: Frequency detector gating period in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FD_GATE_MASK WBGEN2_GEN_MASK(0, 3)
#define HPLL_FBCR_FD_GATE_SHIFT 0
#define HPLL_FBCR_FD_GATE_W(value) WBGEN2_GEN_WRITE(value, 0, 3)
#define HPLL_FBCR_FD_GATE_R(reg) WBGEN2_GEN_READ(reg, 0, 3)
/* definitions for field: Frequency error setpoint in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FERR_SET_MASK WBGEN2_GEN_MASK(4, 12)
#define HPLL_FBCR_FERR_SET_SHIFT 4
#define HPLL_FBCR_FERR_SET_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define HPLL_FBCR_FERR_SET_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for register: HPLL Status Register */
/* definitions for field: Frequency lock in reg: HPLL Status Register */
#define HPLL_PSR_FREQ_LK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Phase lock in reg: HPLL Status Register */
#define HPLL_PSR_PHASE_LK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Loss-of-lock indicator in reg: HPLL Status Register */
#define HPLL_PSR_LOCK_LOST WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
/* definitions for field: Freq/phase error in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_ERR_VAL_MASK WBGEN2_GEN_MASK(0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_SHIFT 0
#define HPLL_RFIFO_R0_ERR_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Freq/phase mode in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_FP_MODE WBGEN2_GEN_MASK(15, 1)
/* definitions for field: DAC output in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_DAC_VAL_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_SHIFT 16
#define HPLL_RFIFO_R0_DAC_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_RFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG HPLL Control Register */
#define HPLL_REG_PCR 0x00000000
/* [0x4]: REG HPLL Divider Register */
#define HPLL_REG_DIVR 0x00000004
/* [0x8]: REG HPLL Frequency Branch Gain Register */
#define HPLL_REG_FBGR 0x00000008
/* [0xc]: REG HPLL Phase Branch Gain Register */
#define HPLL_REG_PBGR 0x0000000c
/* [0x10]: REG HPLL Lock Detect Control Register */
#define HPLL_REG_LDCR 0x00000010
/* [0x14]: REG HPLL Frequency branch control register */
#define HPLL_REG_FBCR 0x00000014
/* [0x18]: REG HPLL Status Register */
#define HPLL_REG_PSR 0x00000018
/* [0x1c]: REG FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_REG_RFIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_REG_RFIFO_CSR 0x00000020
#endif
userspace/include/hw/minic_regs.h 0 → 100644
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/*
Register definitions for slave core: Mini NIC for WhiteRabbit
* File : ../../../software/include/hw/minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Fri Aug 13 02:17:20 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MINI_NIC_WB
#define __WBGEN2_REGDEFS_MINI_NIC_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: miNIC Control Register */
/* definitions for field: TX DMA start in reg: miNIC Control Register */
#define MINIC_MCR_TX_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX DMA idle in reg: miNIC Control Register */
#define MINIC_MCR_TX_IDLE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
/* definitions for register: TX DMA Address */
/* definitions for register: RX DMA Address */
/* definitions for register: RX buffer size register */
/* definitions for register: Debug register */
/* definitions for field: interrupt counter in reg: Debug register */
#define MINIC_DBGR_IRQ_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define MINIC_DBGR_IRQ_CNT_SHIFT 0
#define MINIC_DBGR_IRQ_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define MINIC_DBGR_IRQ_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: status of wb_irq_o line in reg: Debug register */
#define MINIC_DBGR_WB_IRQ_VAL WBGEN2_GEN_MASK(24, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt enable register */
#define MINIC_EIC_IER_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */
/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT 0
#define MINIC_TSFIFO_R0_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */
/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT 0
#define MINIC_TSFIFO_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT 5
#define MINIC_TSFIFO_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 5, 16)
/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x10]: REG Debug register */
#define MINIC_REG_DBGR 0x00000010
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
#define MINIC_REG_EIC_IER 0x00000024
/* [0x28]: REG Interrupt mask register */
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038
#endif
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#ifndef __PHY_CALIBRATION_H
#define __PHY_CALIBRATION_H
#define PHY_CALIBRATE_TX 0
#define PHY_CALIBRATE_RX 1
int shw_cal_init();
int shw_cal_enable_feedback(const char *if_name, int enable, int lane);
int shw_cal_measure(uint32_t *phase); // picoseconds!
int shw_cal_enable_pattern(const char *if_name, int enable);
int shw_poll_dmtd(const char *if_name, uint32_t *phase_ps);
void xpoint_cal_feedback(int on, int port, int txrx);
int xpoint_configure();
#endif
userspace/include/hw/pio.h 0 → 100644
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#ifndef __CPU_IO_H
#define __CPU_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include <at91/at91sam9263.h>
#include <at91/at91_pio.h>
#include <at91/at91_pmc.h>
#include <hw/trace.h>
#define NUM_PIO_BANKS 6
#define PIOA 1
#define PIOB 2
#define PIOC 3
#define PIOD 4
#define PIOE 5
#define PIO_FPGA 6
#define PIO_MODE_GPIO 0
#define PIO_MODE_PERIPH_A 1
#define PIO_MODE_PERIPH_B 2
#define PIO_MODE_PULLUP 0x80
#define PIO_OUT 1
#define PIO_OUT_0 1
#define PIO_OUT_1 2
#define PIO_IN 0
#define _writel(reg, val) *(volatile uint32_t *)(reg) = (val)
#define _readl(reg) (*(volatile uint32_t *)(reg))
typedef struct pio_pin
{
int port;
int pin;
int mode;
int dir;
} pio_pin_t;
#define REG_BASE 0
#define REG_CODR 1
#define REG_SODR 2
#define REG_PDSR 3
extern volatile uint8_t *_sys_base;
extern volatile uint8_t *_pio_base[4][NUM_PIO_BANKS+1];
int shw_pio_init();
void shw_pio_configure(const pio_pin_t *pin);
void shw_pio_configure_pins(const pio_pin_t *pins);
int shw_clock_out_enable(int pck_num, int prescaler, int source);
volatile uint8_t *shw_pio_get_sys_base();
volatile uint8_t *shw_pio_get_port_base(int port);
void shw_set_fp_led(int led, int state);
static inline void shw_pio_set(const pio_pin_t *pin, int state)
{
if(state)
_writel(_pio_base[REG_SODR][pin->port], (1<<pin->pin));
else
_writel(_pio_base[REG_CODR][pin->port], (1<<pin->pin));
}
static inline void shw_pio_set1(const pio_pin_t *pin)
{
//TRACE(TRACE_INFO,"pio_set1 %x\n", _pio_base[REG_SODR][pin->port]);
_writel(_pio_base[REG_SODR][pin->port], (1<<pin->pin));
}
static inline void shw_pio_set0(const pio_pin_t *pin)
{
_writel(_pio_base[REG_CODR][pin->port], (1<<pin->pin));
}
static inline int shw_pio_get(const pio_pin_t *pin)
{
return (_readl(_pio_base[REG_PDSR][pin->port]) & (1<<pin->pin)) ? 1 : 0;
}
static inline int shw_pio_setdir(const pio_pin_t *pin, int dir)
{
if(dir == PIO_OUT)
_writel((_pio_base[REG_BASE][pin->port] + PIO_OER), (1<<pin->pin));
else
_writel((_pio_base[REG_BASE][pin->port] + PIO_ODR), (1<<pin->pin));
return 0;
}
#include "pio_pins.h"
#endif
userspace/include/hw/pio_pins.h 0 → 100644
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#ifndef __PIO_PINS_H
#define __PIO_PINS_H
#include <stdio.h>
#define LED_OFF 0
#define LED_RED 1
#define LED_GREEN 2
#define LED_YELLOW 3
// reset signal for main FPGA
extern const pio_pin_t PIN_main_fpga_nrst[];
extern const pio_pin_t PIN_fled0[];
extern const pio_pin_t PIN_fled1[];
extern const pio_pin_t PIN_fled2[];
extern const pio_pin_t PIN_fled3[];
extern const pio_pin_t PIN_fled4[];
extern const pio_pin_t PIN_fled5[];
extern const pio_pin_t PIN_fled6[];
extern const pio_pin_t PIN_fled7[];
// uTCA front panel LEDs
extern const pio_pin_t PIN_uled0[];
extern const pio_pin_t PIN_uled1[];
extern const pio_pin_t PIN_uled2[];
extern const pio_pin_t PIN_uled3[];
// AD9516 PLL control signals
extern const pio_pin_t PIN_ad9516_cs[];
extern const pio_pin_t PIN_ad9516_sclk[];
extern const pio_pin_t PIN_ad9516_sdio[];
extern const pio_pin_t PIN_ad9516_sdo[];
extern const pio_pin_t PIN_ad9516_refsel[];
extern const pio_pin_t PIN_ad9516_nrst[];
// uTCA Hotswap switch
extern const pio_pin_t PIN_hotswap_switch[];
// main FPGA passive serial configuration signals
extern const pio_pin_t PIN_main_fpga_dclk[];
extern const pio_pin_t PIN_main_fpga_nconfig[];
extern const pio_pin_t PIN_main_fpga_data[];
extern const pio_pin_t PIN_main_fpga_nstatus[];
extern const pio_pin_t PIN_main_fpga_confdone[];
// clocking board FPGA passive serial configuration signals
extern const pio_pin_t PIN_clkb_fpga_dclk[];
extern const pio_pin_t PIN_clkb_fpga_nconfig[];
extern const pio_pin_t PIN_clkb_fpga_data[];
extern const pio_pin_t PIN_clkb_fpga_nstatus[];
extern const pio_pin_t PIN_clkb_fpga_confdone[];
extern const pio_pin_t PIN_clkb_fpga_nrst[];
extern const pio_pin_t PIN_up0_sfp_sda[];
extern const pio_pin_t PIN_up0_sfp_scl[];
extern const pio_pin_t PIN_up0_sfp_los[];
extern const pio_pin_t PIN_up0_sfp_tx_fault[];
extern const pio_pin_t PIN_up0_sfp_tx_disable[];
extern const pio_pin_t PIN_up0_sfp_detect[];
extern const pio_pin_t PIN_up1_sfp_sda[];
extern const pio_pin_t PIN_up1_sfp_scl[];
extern const pio_pin_t PIN_up1_sfp_los[];
extern const pio_pin_t PIN_up1_sfp_tx_fault[];
extern const pio_pin_t PIN_up1_sfp_tx_disable[];
extern const pio_pin_t PIN_up1_sfp_detect[];
extern const pio_pin_t * _all_cpu_gpio_pins[];
extern const pio_pin_t * _all_fpga_gpio_pins[];
extern const pio_pin_t * _fp_leds[];
#endif
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