Set correct value for our DDR: MT47H32M16HR

usb-loader/samba_applets/at91lib/boards/at91sam9g45-ek/board_memories.c

@@ -135,7 +135,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
             // 4. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR.            
 
             WRITE(pDdrc, HDDRSDRC2_CR, AT91C_DDRC2_NC_DDR10_SDR9  |     // 10 column bits (1K)
-                                       AT91C_DDRC2_NR_14          |     // 14 row bits    (8K)
+                                       AT91C_DDRC2_NR_13          |     // 14 row bits    (8K)
                                        AT91C_DDRC2_CAS_3          |     // CAS Latency 3
                                        AT91C_DDRC2_DLL_RESET_DISABLED
                                        ); // DLL not reset
@@ -146,7 +146,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
                                          AT91C_DDRC2_TWR_2        |     //  2 * 7.5 = 15 ns
                                          AT91C_DDRC2_TRC_8        |     //  8 * 7.5 = 60 ns
                                          AT91C_DDRC2_TRP_2        |     //  2 * 7.5 = 15 ns
-                                         AT91C_DDRC2_TRRD_1       |     //  1 * 7.5 = 7.5 ns
+                                         AT91C_DDRC2_TRRD_2       |     //  2 * 7.5 = 15 ns
                                          AT91C_DDRC2_TWTR_1       |     //  1 clock cycle
                                          AT91C_DDRC2_TMRD_2);           //  2 clock cycles
 
@@ -156,8 +156,8 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
                                          AT91C_DDRC2_TRFC_14 << 0);     // 14 * 7.5 = 105 ns (must be 105 ns for 512M DDR)
 
             WRITE(pDdrc, HDDRSDRC2_T2PR, AT91C_DDRC2_TRTP_1   |         //  1 * 7.5 = 7.5 ns
-                                         AT91C_DDRC2_TRPA_0   |         
-                                         AT91C_DDRC2_TXARDS_7 |         //  7 clock cycles
+                                         AT91C_DDRC2_TRPA_2   |         
+                                         AT91C_DDRC2_TXARDS_8 |         //  7 clock cycles
                                          AT91C_DDRC2_TXARD_2);          //  2 clock cycles
 
             // Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock.