Schematics:
------------

* C165 value changed from 100nF to 220nF
* VCC_IN of CDCM61002 (IC13) connected to +3V3
* RSTN pin of IC13 conected to a 47nF capacitor, not to +3V3
* QDRII_200CLK moved to OUT3 (LVPECL) of AD9516.
* Added LVDS termination resistor to adapt OUT3 to LVDS format
* CLK_OUT (EXTREF125MHZOUT) connected to OUT9 (CMOS) of AD9516-4.
* CLK_OUT transformer changed by 1:1 (WBC1-1LB)
* R253 and R254 resistor (Ethernet sheet) changed to 0402 size in order
to reduce items.
* Changed EXTPPSIN input stage in order to add 50 R termination
selectable by the FPGA.
* Name of nets QDRII_CLK and QDRII_200CLK changed to REF_CLK and
AUX_CLK.
* Input EXTREF_125M removed.
* QDRII IC42 chip removed.
* Added ouput from FPGA latched by an AD9516 clock. This output uses
the EXTREF_125M SMC connector:
	* Added LVPECL latch
	* Added LVPECL to LVTTL translator at the output
	* CLK0 input of IC12 changed to OUT6 of AD9516
	* FPGA VCCO Bank 26 changed to +2V5 to use LVPECL and LVDS
* Removed the six 0R resistor at the inputs of the AD5662 DACs
* FPGA Banks 26, 36 and 25 moved to "PFGA_Peripherals_Control" sheet.
* Connected the 3 free buffers SN74LVT125DW to the EXTPPSOUT output
signal.

PCB:
------

* GTX_DIFF signals routed on 90um/160um in order to reduce space,
allowing to pass between vias
* Some vias were moved from pads of some components to avoid the solder
paste flooding by the vía.
* IVT3200 VCO was moved to separate it of NAND Flash IC

Remove miniBackplane_SFP which was a copy of v3.2
Rename miniBackplane_18Ports_SFP_V3.3/ to mini_backplane_18SFP/
Rename miniBackplane_test/ to mini_backplane_test/

Fans connector changed by the P/N 61900211121 of Würth

Chassis hole for SCB changed, it was bad.
o.c. capacitor C42 between Chassis and a hole removed.

Clearance of polygon increased up to 0.2 mm (PCB manufacturing requirement)

PCB assembler suggestions added.

PCB assembler suggestions added.

1.- SCB_PLLs: C165 footprint changed to 0402 in order to remove this component and reduce boom.
2.- Connectors:CN1 Ethernet connector case connected to GND_SHIELD.
3.- CPU_100M_Ethernet:C206 changed from 470pF to 2,7nF in order to remove this component and reduce boom.Added R253 and R254 resistors (both 75R) between the Tr1 and C214.
L10 is not mounted now. It connects GND_SHIELD and GND_ETH.
4.- QDRII_mem and QDRII_power: All the components of the QDRII memories will be not mounted.