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Commit f07ce20d authored by tomaszwlostowski's avatar tomaszwlostowski
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circuit_board/MCH_MAIN/MB_CPU_io_ports.SchDocPreview
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circuit_board/MCH_MAIN/MB_CPU_memory.SchDocPreview
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circuit_board/MCH_MAIN/MB_ZBT_memory.SchDocPreview
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circuit_board/MCH_MAIN/MB_fpga_power.SchDoc
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circuit_board/MCH_MAIN/MB_fpga_power.SchDocPreview
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circuit_board/MCH_MAIN/MB_main.SchDoc
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circuit_board/MCH_MAIN/MB_main.SchDocPreview
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circuit_board/MCH_MAIN/MB_main_FPGA.SchDoc
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circuit_board/MCH_MAIN/MB_main_FPGA.SchDocPreview
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circuit_board/MCH_MAIN/MB_power_supply.SchDocPreview
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circuit_board/MCH_MAIN/MCH_MAIN.PCBDOC
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circuit_board/MCH_MAIN/MCH_MAIN.PrjPcb
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circuit_board/MCH_MAIN/MCH_MAIN.PrjPcbStructure
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Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=CPU|SchDesignator=CPU|FileName=MB_CPU_io_ports.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_io_ports.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP0|SchDesignator=DP0|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP1|SchDesignator=DP1|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP2|SchDesignator=DP2|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP3|SchDesignator=DP3|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP4|SchDesignator=DP4|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP5|SchDesignator=DP5|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP6|SchDesignator=DP6|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP7|SchDesignator=DP7|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=MB_main_FPGA.SchDoc|SymbolType=Normal|RawFileName=MB_main_FPGA.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=LETH|SchDesignator=LETH|FileName=MB_CPU_100m_ethernet.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_100m_ethernet.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=SENS|SchDesignator=SENS|FileName=MB_sensors.SchDoc|SymbolType=Normal|RawFileName=MB_sensors.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_clocking|SchDesignator=U_MB_clocking|FileName=MB_clocking.SchDoc|SymbolType=Normal|RawFileName=MB_clocking.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_CPU_memory|SchDesignator=U_MB_CPU_memory|FileName=MB_CPU_memory.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_memory.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_fpga_power|SchDesignator=U_MB_fpga_power|FileName=MB_fpga_power.SchDoc|SymbolType=Normal|RawFileName=MB_fpga_power.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_power_supply|SchDesignator=U_MB_power_supply|FileName=MB_power_supply.SchDoc|SymbolType=Normal|RawFileName=MB_power_supply.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_ZBT_memory|SchDesignator=U_MB_ZBT_memory|FileName=MB_ZBT_memory.SchDoc|SymbolType=Normal|RawFileName=MB_ZBT_memory.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=WD|SchDesignator=WD|FileName=MB_watchdog_mcu.SchDoc|SymbolType=Normal|RawFileName=MB_watchdog_mcu.SchDoc|ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=CPU|SchDesignator=CPU|FileName=MB_CPU_io_ports.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_io_ports.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP0|SchDesignator=DP0|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP1|SchDesignator=DP1|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP2|SchDesignator=DP2|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP3|SchDesignator=DP3|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP4|SchDesignator=DP4|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP5|SchDesignator=DP5|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP6|SchDesignator=DP6|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=DP7|SchDesignator=DP7|FileName=MB_downlink_phy.SchDoc|SymbolType=Normal|RawFileName=MB_downlink_phy.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=MB_main_FPGA.SchDoc|SymbolType=Normal|RawFileName=MB_main_FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=LETH|SchDesignator=LETH|FileName=MB_CPU_100m_ethernet.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_100m_ethernet.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=SENS|SchDesignator=SENS|FileName=MB_sensors.SchDoc|SymbolType=Normal|RawFileName=MB_sensors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_clocking|SchDesignator=U_MB_clocking|FileName=MB_clocking.SchDoc|SymbolType=Normal|RawFileName=MB_clocking.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_CPU_memory|SchDesignator=U_MB_CPU_memory|FileName=MB_CPU_memory.SchDoc|SymbolType=Normal|RawFileName=MB_CPU_memory.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_fpga_power|SchDesignator=U_MB_fpga_power|FileName=MB_fpga_power.SchDoc|SymbolType=Normal|RawFileName=MB_fpga_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_power_supply|SchDesignator=U_MB_power_supply|FileName=MB_power_supply.SchDoc|SymbolType=Normal|RawFileName=MB_power_supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=U_MB_ZBT_memory|SchDesignator=U_MB_ZBT_memory|FileName=MB_ZBT_memory.SchDoc|SymbolType=Normal|RawFileName=MB_ZBT_memory.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=MB_main.SchDoc|Designator=WD|SchDesignator=WD|FileName=MB_watchdog_mcu.SchDoc|SymbolType=Normal|RawFileName=MB_watchdog_mcu.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=MB_main.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC12|DocumentName=MB_main_FPGA.SchDoc|LibraryReference=EP3C120F780C7|SubProjectPath= |Configuration= |Description=Cyclone III Family FPGA, 531 I/O Pins, 4 PLLs, 780-Pin FBGA, Speed Grade 7, Commercial Grade|SubPartUniqueId1=EGAPETLP|SubPartDocPath1=MB_main_FPGA.SchDoc|SubPartUniqueId2=GRKUQEYM|SubPartDocPath2=MB_main_FPGA.SchDoc|SubPartUniqueId3=LMOYTUSG|SubPartDocPath3=MB_main_FPGA.SchDoc|SubPartUniqueId4=JWMXECIW|SubPartDocPath4=MB_main_FPGA.SchDoc|SubPartUniqueId5=PQBXOWHI|SubPartDocPath5=MB_main_FPGA.SchDoc|SubPartUniqueId6=AYPWGOXG|SubPartDocPath6=MB_main_FPGA.SchDoc|SubPartUniqueId7=NGNKRPJI|SubPartDocPath7=MB_main_FPGA.SchDoc|SubPartUniqueId8=DQPDTACF|SubPartDocPath8=MB_main_FPGA.SchDoc|SubPartUniqueId9=EHCTYWHU|SubPartDocPath9=MB_main_FPGA.SchDoc|SubPartUniqueId10=PAFWOFIU|SubPartDocPath10=MB_fpga_power.SchDoc|SubPartUniqueId11=MFSJOFFR|SubPartDocPath11=MB_fpga_power.SchDoc|SubPartUniqueId12=PIPKAPAR|SubPartDocPath12=MB_fpga_power.SchDoc|SubPartUniqueId13=STUJSJAY|SubPartDocPath13=MB_fpga_power.SchDoc
circuit_board/common/libs/footprints.PCBLIB
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circuit_board/common/libs/wr_switch.SCHLIB
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