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circuit_board/MCH_CLKB/MCH_CLKB.AnnotationPreview

 [Preview]
-LargeImageOriginalSize=698000
-LargeImageWidth=349
+LargeImageOriginalSize=706000
+LargeImageWidth=353
 LargeImageHeight=500
-LargeImage=78DAEDC3410D00000C03A1F9377D73D117245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB30FD20F6670
-MediumImageOriginalSize=174000
-MediumImageWidth=174
+LargeImage=78DAEDC3410D00000C03A1F9377D73D117245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEAF0033E98C059
+MediumImageOriginalSize=177000
+MediumImageWidth=177
 MediumImageHeight=250
-MediumImage=78DAEDC3410D00000C03A1F9377D73D117245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8E3EBE1CE3F2
-SmallImageOriginalSize=63000
-SmallImageWidth=105
+MediumImage=78DAEDC3410D00000C03A1F9377DFB5406245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEE037262A5AF
+SmallImageOriginalSize=63600
+SmallImageWidth=106
 SmallImageHeight=150
-SmallImage=78DAEDC3410D00000C03A1F9377DD3D03F245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEAF001B672E428
+SmallImage=78DAEDC3410D00000C03A1F9377D93D10F245497AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8E3FBB52A484
 

circuit_board/MCH_CLKB/MCH_CLKB.PrjPcb

@@ -164,6 +164,20 @@ ClassGenCCAutoEnabled=1
 ClassGenCCAutoRoomEnabled=1
 ClassGenNCAutoScope=None
 
+[Document11]
+DocumentPath=MCH_CLKB.OutJob
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+
 [Generic_SCH]
 Collation=True
 Copies=1
@@ -188,7 +202,7 @@ AutoOpenOutJob=-1
 [Generic_SmartPDFSettings]
 ProjectMode=-1
 ZoomPrecision=50
-AddNetsInformation=0
+AddNetsInformation=-1
 AddNetPins=-1
 AddNetNetLabels=-1
 AddNetPorts=-1
@@ -200,7 +214,7 @@ SCH_PrintColor=0
 SCH_ShowNoErc=-1
 SCH_ShowParameter=-1
 SCH_ShowProbes=-1
-OutputFileName=MCH_CLKB.PrjPcb=E:\WhiteRabbit-svn\trunk\circuit_board\MCH_CLKB\MCH_CLKB.pdf
+OutputFileName=MCH_CLKB.PrjPcb=D:\projects\whiterabbit\trunk\circuit_board\MCH_CLKB\MCH_CLKB.pdf
 SCH_ExpandLogicalToPhysical=0
 SCH_VariantName=[None]
 SCH_ExpandComponentDesignators=-1

circuit_board/MCH_CLKB/MCH_CLKB.PrjPcbStructure

-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=APD|SchDesignator=APD|FileName=CLKB_analog_phase_detector.SchDoc|SymbolType=Normal|RawFileName=CLKB_analog_phase_detector.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=CLK|SchDesignator=CLK|FileName=CLKB_clocking_system.SchDoc|SymbolType=Normal|RawFileName=CLKB_clocking_system.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=CLKB_clocking_fpga.SchDoc|SymbolType=Normal|RawFileName=CLKB_clocking_fpga.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=PWR|SchDesignator=PWR|FileName=CLKB_power_regulators.SchDoc|SymbolType=Normal|RawFileName=CLKB_power_regulators.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=RS232|SchDesignator=RS232|FileName=CLKB_RS232_port.SchDoc|SymbolType=Normal|RawFileName=CLKB_RS232_port.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=SENS|SchDesignator=SENS|FileName=CLKB_temp_sensors.SchDoc|SymbolType=Normal|RawFileName=CLKB_temp_sensors.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=SMI|SchDesignator=SMI|FileName=CLKB_SMI_if_1_6.SchDoc|SymbolType=Normal|RawFileName=CLKB_SMI_if_1_6.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=up0|SchDesignator=up0|FileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|SymbolType=Normal|RawFileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|ObjectKind=Sheet Symbol
-Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=up1|SchDesignator=up1|FileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|SymbolType=Normal|RawFileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=APD|SchDesignator=APD|FileName=CLKB_analog_phase_detector.SchDoc|SymbolType=Normal|RawFileName=CLKB_analog_phase_detector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=CLK|SchDesignator=CLK|FileName=CLKB_clocking_system.SchDoc|SymbolType=Normal|RawFileName=CLKB_clocking_system.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=FPGA|SchDesignator=FPGA|FileName=CLKB_clocking_fpga.SchDoc|SymbolType=Normal|RawFileName=CLKB_clocking_fpga.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=PWR|SchDesignator=PWR|FileName=CLKB_power_regulators.SchDoc|SymbolType=Normal|RawFileName=CLKB_power_regulators.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=RS232|SchDesignator=RS232|FileName=CLKB_RS232_port.SchDoc|SymbolType=Normal|RawFileName=CLKB_RS232_port.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=SENS|SchDesignator=SENS|FileName=CLKB_temp_sensors.SchDoc|SymbolType=Normal|RawFileName=CLKB_temp_sensors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=SMI|SchDesignator=SMI|FileName=CLKB_SMI_if_1_6.SchDoc|SymbolType=Normal|RawFileName=CLKB_SMI_if_1_6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=up0|SchDesignator=up0|FileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|SymbolType=Normal|RawFileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
+Record=SheetSymbol|SourceDocument=CLKB_main.SchDoc|Designator=up1|SchDesignator=up1|FileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|SymbolType=Normal|RawFileName=CLKB_uplink_phy_and_sfp_1221.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
 Record=TopLevelDocument|FileName=CLKB_main.SchDoc
 Record=FPGA_COMPONENT|BaseComponentDesignator=IC5|DocumentName=CLKB_clocking_fpga.SchDoc|LibraryReference=EP3C5E144C7|SubProjectPath= |Configuration= |Description=Cyclone III Family FPGA, 94 I/O Pins, 4 PLLs, 144-Pin EQFP, Speed Grade 7, Commercial Grade|SubPartUniqueId1=GKAXHKTY|SubPartDocPath1=CLKB_clocking_fpga.SchDoc|SubPartUniqueId2=JQFDDHBX|SubPartDocPath2=CLKB_clocking_fpga.SchDoc|SubPartUniqueId3=UCAHDKEH|SubPartDocPath3=CLKB_clocking_fpga.SchDoc|SubPartUniqueId4=LFOKBKOR|SubPartDocPath4=CLKB_clocking_fpga.SchDoc|SubPartUniqueId5=BUNBBNUY|SubPartDocPath5=CLKB_clocking_fpga.SchDoc|SubPartUniqueId6=LOAEVQVY|SubPartDocPath6=CLKB_clocking_fpga.SchDoc|SubPartUniqueId7=TFMDBRGA|SubPartDocPath7=CLKB_clocking_fpga.SchDoc|SubPartUniqueId8=ANRIMXBJ|SubPartDocPath8=CLKB_clocking_fpga.SchDoc

circuit_board/MCH_MAIN/MCH_MAIN.PrjPcb

@@ -206,6 +206,20 @@ ClassGenCCAutoEnabled=1
 ClassGenCCAutoRoomEnabled=1
 ClassGenNCAutoScope=None
 
+[Document14]
+DocumentPath=MCH_MAIN.OutJob
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+
 [GeneratedDocument1]
 DocumentPath=Project Outputs for MCH_MAIN\Design Rule Check - MCH_MAIN.html
 
@@ -233,19 +247,19 @@ AutoOpenOutJob=-1
 [Generic_SmartPDFSettings]
 ProjectMode=-1
 ZoomPrecision=50
-AddNetsInformation=0
+AddNetsInformation=-1
 AddNetPins=-1
 AddNetNetLabels=-1
 AddNetPorts=-1
 ExportBOM=0
-TemplateFilename=
+TemplateFilename=BOM Default Template.XLT
 TemplateStoreRelative=-1
 PCB_PrintColor=0
 SCH_PrintColor=0
 SCH_ShowNoErc=-1
 SCH_ShowParameter=-1
 SCH_ShowProbes=-1
-OutputFileName=MCH_MAIN.PrjPcb=E:\WhiteRabbit-svn\trunk\circuit_board\MCH_MAIN\MCH_MAIN.pdf
+OutputFileName=MCH_MAIN.PrjPcb=D:\projects\whiterabbit\trunk\circuit_board\MCH_MAIN\MCH_MAIN.pdf
 SCH_ExpandLogicalToPhysical=0
 SCH_VariantName=[None]
 SCH_ExpandComponentDesignators=-1