The I2C interface needs a serious redesign:

PS_MIOS:

• The I2C_MUX_(SCL|SDA) signals are not driven by any source. Same for I2C_MUX_RESETB
• If I presume correctly, the idea is to drive the I2C busses from the PS I2C controller and then a series of multiplexers.
• I2C muxing is difficult and reduces the bandwidth available for the chips. We had lots of troubles getting it right in the AFCZ board, so unless we have very few pins in the FPGA PL available, I would advise against it and have more independent controllers, driving dedicated busses in the PL.

Here's the proposed I2C bus layout:

PS I2C:

• DDR4 SPD (J1)
• EEPROM (IC12)
• Power (IC25/IC29/IC32).
• Fan control (U9)
• Current (IC43) / temperature sensors (IC37 and friends)
• (maybe) the management SFP

PL I2C (each of the lines requires a separate I2C bus)

• Each of the WR SFPs (if we're really low on PL pins, the SFPs can use a multiplexer, but generally I would prefer to avoid it). Please check the issue about SFP signals/LEDs too for ideas how to free up some pins.
• OLED LCD (requires a separate interface to avoid refresh issues when shared with other devices)
• Si549
• Helper VCXO (this one is critical as it must be closed-loop controlled by the RTS/SoftPLL).