Clocking circuit - check determinism of HMC7044, feed 10MHz directly to HMC7044
- HMC7044, did you actually check phase determinism? If not, verify with an EVAL-HMC7044 evaluation board.
- Phase determinism is critical. When you operate in master- or grand master mode your WR CLK (generated by the HMC7044) must be deterministic phase aligned with your external reference. To my opinion the 10MHz in (i.e. Sine or Digital CLK AUX IN SMA) can be connected to the HMC7044 as reference clock, just like the "optional 10MHz from te expansion board". So, no need for a LMX2594. And a as a bonus: you get a very clean WR CLK (without routing through the phase noisy FPGA).
- The (super clean) external 10 MHz should be used to create a clean 62.5/125 MHz WR_CLK without FPGA intervention to avoid additional phase noise. So the external 10MHz reference should be input to the HMC7044.