Commit f9e04b52 authored by Maciej Lipinski's avatar Maciej Lipinski

swcore: changed name: rtu_rsp_ack_o->rtu_ack_o

parent cab76b33
......@@ -113,7 +113,7 @@ entity swc_core is
-- rtu_drop_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rtu_prio_i : in std_logic_vector(c_swc_num_ports * c_swc_prio_width - 1 downto 0)
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
rtu_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end swc_core;
......@@ -314,7 +314,7 @@ architecture rtl of swc_core is
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_ack_o => rtu_rsp_ack_o(i),
rtu_rsp_ack_o => rtu_ack_o(i),
rtu_rsp_valid_i => rtu_rsp_i(i).valid,
rtu_dst_port_mask_i => rtu_rsp_i(i).port_mask(c_swc_num_ports - 1 downto 0),
rtu_drop_i => rtu_rsp_i(i).drop,
......
......@@ -82,7 +82,7 @@ entity xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
rtu_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end xswc_core;
......@@ -115,7 +115,7 @@ architecture rtl of xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
rtu_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end component;
......@@ -140,6 +140,6 @@ begin
src_o => src_o,
rtu_rsp_i => rtu_rsp_i,
rtu_rsp_ack_o => rtu_rsp_ack_o);
rtu_ack_o => rtu_ack_o);
end rtl;
......@@ -268,7 +268,7 @@ component xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
rtu_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end component;
......@@ -300,7 +300,7 @@ U_xswc_core: xswc_core
src_o => src_o,
rtu_rsp_i => rtu_rsp_i,
rtu_rsp_ack_o => rtu_rsp_ack_o
rtu_ack_o => rtu_rsp_ack_o
);
rtu: for i in 0 to g_swc_num_ports -1 generate
......
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