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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
f9e04b52
Commit
f9e04b52
authored
Jan 22, 2012
by
Maciej Lipinski
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swcore: changed name: rtu_rsp_ack_o->rtu_ack_o
parent
cab76b33
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3 changed files
with
7 additions
and
7 deletions
+7
-7
swc_core.vhd
modules/wrsw_swcore/swc_core.vhd
+2
-2
xswc_core.vhd
modules/wrsw_swcore/xswc_core.vhd
+3
-3
xswc_core_7_ports_wrapper.vhd
testbench/swcore/xswc_core_7_ports_wrapper.vhd
+2
-2
No files found.
modules/wrsw_swcore/swc_core.vhd
View file @
f9e04b52
...
...
@@ -113,7 +113,7 @@ entity swc_core is
-- rtu_drop_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rtu_prio_i : in std_logic_vector(c_swc_num_ports * c_swc_prio_width - 1 downto 0)
rtu_rsp_i
:
in
t_rtu_response_array
(
c_swc_num_ports
-
1
downto
0
);
rtu_
rsp_ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
rtu_
ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
);
end
swc_core
;
...
...
@@ -314,7 +314,7 @@ architecture rtl of swc_core is
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_ack_o
=>
rtu_
rsp_
ack_o
(
i
),
rtu_rsp_ack_o
=>
rtu_ack_o
(
i
),
rtu_rsp_valid_i
=>
rtu_rsp_i
(
i
)
.
valid
,
rtu_dst_port_mask_i
=>
rtu_rsp_i
(
i
)
.
port_mask
(
c_swc_num_ports
-
1
downto
0
),
rtu_drop_i
=>
rtu_rsp_i
(
i
)
.
drop
,
...
...
modules/wrsw_swcore/xswc_core.vhd
View file @
f9e04b52
...
...
@@ -82,7 +82,7 @@ entity xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i
:
in
t_rtu_response_array
(
c_swc_num_ports
-
1
downto
0
);
rtu_
rsp_ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
rtu_
ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
);
end
xswc_core
;
...
...
@@ -115,7 +115,7 @@ architecture rtl of xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i
:
in
t_rtu_response_array
(
c_swc_num_ports
-
1
downto
0
);
rtu_
rsp_ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
rtu_
ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
);
end
component
;
...
...
@@ -140,6 +140,6 @@ begin
src_o
=>
src_o
,
rtu_rsp_i
=>
rtu_rsp_i
,
rtu_
rsp_ack_o
=>
rtu_rsp
_ack_o
);
rtu_
ack_o
=>
rtu
_ack_o
);
end
rtl
;
testbench/swcore/xswc_core_7_ports_wrapper.vhd
View file @
f9e04b52
...
...
@@ -268,7 +268,7 @@ component xswc_core is
-------------------------------------------------------------------------------
rtu_rsp_i
:
in
t_rtu_response_array
(
c_swc_num_ports
-
1
downto
0
);
rtu_
rsp_ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
rtu_
ack_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
)
);
end
component
;
...
...
@@ -300,7 +300,7 @@ U_xswc_core: xswc_core
src_o
=>
src_o
,
rtu_rsp_i
=>
rtu_rsp_i
,
rtu_
rsp_
ack_o
=>
rtu_rsp_ack_o
rtu_ack_o
=>
rtu_rsp_ack_o
);
rtu
:
for
i
in
0
to
g_swc_num_ports
-1
generate
...
...
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