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White Rabbit Switch - Gateware
Commit cab76b33 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore: changed rtu interface to types (in shared_types_pkg)

parent eb06a98a
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Showing with 41 additions and 203 deletions
modules/wrsw_swcore/Manifest.py
View file @ cab76b33
......@@ -31,4 +31,5 @@ files = [
"xswc_core.vhd",
"xswc_output_block.vhd",
"xswc_input_block.vhd",
"../wrsw_shared_types_pkg.vhd",
]
\ No newline at end of file
modules/wrsw_swcore/swc_core.vhd
View file @ cab76b33
......@@ -48,6 +48,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity swc_core is
generic(
......@@ -106,11 +107,13 @@ entity swc_core is
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
rtu_dst_port_mask_i : in std_logic_vector(c_swc_num_ports * c_swc_num_ports - 1 downto 0);
rtu_drop_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
rtu_prio_i : in std_logic_vector(c_swc_num_ports * c_swc_prio_width - 1 downto 0)
-- rtu_rsp_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rtu_dst_port_mask_i : in std_logic_vector(c_swc_num_ports * c_swc_num_ports - 1 downto 0);
-- rtu_drop_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rtu_prio_i : in std_logic_vector(c_swc_num_ports * c_swc_prio_width - 1 downto 0)
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end swc_core;
......@@ -311,11 +314,17 @@ architecture rtl of swc_core is
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i => rtu_rsp_valid_i(i),
rtu_rsp_ack_o => rtu_rsp_ack_o(i),
rtu_dst_port_mask_i => rtu_dst_port_mask_i((i + 1) * c_swc_num_ports -1 downto i * c_swc_num_ports),
rtu_drop_i => rtu_drop_i(i),
rtu_prio_i => rtu_prio_i((i + 1) * c_swc_prio_width -1 downto i * c_swc_prio_width),
rtu_rsp_ack_o => rtu_rsp_ack_o(i),
rtu_rsp_valid_i => rtu_rsp_i(i).valid,
rtu_dst_port_mask_i => rtu_rsp_i(i).port_mask(c_swc_num_ports - 1 downto 0),
rtu_drop_i => rtu_rsp_i(i).drop,
rtu_prio_i => rtu_rsp_i(i).prio,
-- rtu_rsp_valid_i => rtu_rsp_valid_i(i),
-- rtu_rsp_ack_o => rtu_rsp_ack_o(i),
-- rtu_dst_port_mask_i => rtu_dst_port_mask_i((i + 1) * c_swc_num_ports -1 downto i * c_swc_num_ports),
-- rtu_drop_i => rtu_drop_i(i),
-- rtu_prio_i => rtu_prio_i((i + 1) * c_swc_prio_width -1 downto i * c_swc_prio_width),
-------------------------------------------------------------------------------
-- I/F with Multiport Memory (MPU)
-------------------------------------------------------------------------------
......
modules/wrsw_swcore/xswc_core.vhd
View file @ cab76b33
This diff is collapsed.
testbench/swcore/xswc_core_7_ports_wrapper.vhd
View file @ cab76b33
......@@ -48,6 +48,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity xswc_core_7_ports_wrapper is
generic
......@@ -266,11 +267,8 @@ component xswc_core is
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i : in std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_dst_port_mask_i : in std_logic_vector(g_swc_num_ports * g_swc_num_ports - 1 downto 0);
rtu_drop_i : in std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_prio_i : in std_logic_vector(g_swc_num_ports * g_swc_prio_width - 1 downto 0)
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
);
end component;
......@@ -281,6 +279,8 @@ end component;
signal src_i : t_wrf_source_in_array(g_swc_num_ports-1 downto 0);
signal src_o : t_wrf_source_out_array(g_swc_num_ports-1 downto 0);
signal rtu_rsp_i : t_rtu_response_array(c_swc_num_ports - 1 downto 0);
begin
U_xswc_core: xswc_core
......@@ -299,15 +299,17 @@ U_xswc_core: xswc_core
src_i => src_i,
src_o => src_o,
rtu_rsp_valid_i => rtu_rsp_valid_i,
rtu_rsp_ack_o => rtu_rsp_ack_o,
rtu_dst_port_mask_i => rtu_dst_port_mask_i,
rtu_drop_i => rtu_drop_i,
rtu_prio_i => rtu_prio_i
rtu_rsp_i => rtu_rsp_i,
rtu_rsp_ack_o => rtu_rsp_ack_o
);
rtu: for i in 0 to g_swc_num_ports -1 generate
rtu_rsp_i(i).valid <= rtu_rsp_valid_i(i);
rtu_rsp_i(i).port_mask( c_RTU_MAX_PORTS- 1 downto g_swc_num_ports)<= (others => '0');
rtu_rsp_i(i).port_mask(g_swc_num_ports - 1 downto 0) <= rtu_dst_port_mask_i((i+1)*g_swc_num_ports - 1 downto i*g_swc_num_ports);
rtu_rsp_i(i).prio <= rtu_prio_i((i+1)*g_swc_prio_width -1 downto i*g_swc_prio_width);
rtu_rsp_i(i).drop <= rtu_drop_i(i);
end generate;
snk_i(0).dat <= snk_dat_0_i;
snk_i(0).adr <= snk_adr_0_i;
......
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