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White Rabbit Switch - Gateware
Commits
f0a792fa
Commit
f0a792fa
authored
Jul 24, 2012
by
Tomasz Wlostowski
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testbench/scb_top: wip
parent
6c650238
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5 changed files
with
123 additions
and
17 deletions
+123
-17
simdrv_txtsu.svh
sim/simdrv_txtsu.svh
+58
-0
txtsu_regs.v
sim/txtsu_regs.v
+32
-0
main.sv
testbench/scb_top/main.sv
+30
-14
scb_top_sim_svwrap.svh
testbench/scb_top/scb_top_sim_svwrap.svh
+1
-1
simdrv_wr_endpoint.svh
testbench/scb_top/simdrv_wr_endpoint.svh
+2
-2
No files found.
sim/simdrv_txtsu.svh
0 → 100644
View file @
f0a792fa
`ifndef
__
SIMDRV_WR_TXTSU_SVH
`define
__SIMDRV_WR_TXTSU_SVH 1
`timescale
1
ns
/
1
ps
`include
"simdrv_defs.svh"
`include
"regs/txtsu_regs.vh"
class
CSimDrv_TXTSU
;
CBusAccessor
acc_regs
;
uint64_t
base_addr
;
function
new
(
CBusAccessor
regs_
,
uint64_t
base_addr_
)
;
base_addr
=
base_addr_
;
acc_regs
=
regs_
;
endfunction
// new
task
init
()
;
writel
(
`ADDR_TXTSU_EIC_IER
,
1
)
;
endtask
// init
task
writel
(
uint32_t
addr
,
uint32_t
val
)
;
acc_regs
.
write
(
base_addr
+
addr
,
val
,
4
)
;
endtask
// writel
task
readl
(
uint32_t
addr
,
output
uint32_t
val
)
;
uint64_t
tmp
;
acc_regs
.
read
(
base_addr
+
addr
,
tmp
,
4
)
;
val
=
tmp
;
endtask
// readl
task
update
(
bit
txts_irq
)
;
uint32_t
csr
,
r0
,
r1
,
r2
;
if
(
!
txts_irq
)
return
;
while
(
1
)
begin
readl
(
`ADDR_TXTSU_TSF_CSR
,
csr
)
;
if
(
csr
&
`TXTSU_TSF_CSR_EMPTY
)
break
;
readl
(
`ADDR_TXTSU_TSF_R0
,
r0
)
;
readl
(
`ADDR_TXTSU_TSF_R1
,
r1
)
;
readl
(
`ADDR_TXTSU_TSF_R2
,
r2
)
;
$
display
(
"txtsu: val %x pid %d fid %d incorrect %1b"
,
r0
,
r1
&
'h1f
,
r1
>>
16
,
r2
&
1
)
;
end
// while (1)
endtask
// update
endclass
`endif
// `ifndef __SIMDRV_WR_TXTSU_SVH
sim/txtsu_regs.v
0 → 100644
View file @
f0a792fa
`define
ADDR_TXTSU_EIC_IDR
5'h0
`define
TXTSU_EIC_IDR_NEMPTY_OFFSET 0
`define
TXTSU_EIC_IDR_NEMPTY 32
'
h00000001
`define
ADDR_TXTSU_EIC_IER 5
'
h4
`define
TXTSU_EIC_IER_NEMPTY_OFFSET 0
`define
TXTSU_EIC_IER_NEMPTY 32
'
h00000001
`define
ADDR_TXTSU_EIC_IMR 5
'
h8
`define
TXTSU_EIC_IMR_NEMPTY_OFFSET 0
`define
TXTSU_EIC_IMR_NEMPTY 32
'
h00000001
`define
ADDR_TXTSU_EIC_ISR 5
'
hc
`define
TXTSU_EIC_ISR_NEMPTY_OFFSET 0
`define
TXTSU_EIC_ISR_NEMPTY 32
'
h00000001
`define
ADDR_TXTSU_TSF_R0 5
'
h10
`define
TXTSU_TSF_R0_VAL_R_OFFSET 0
`define
TXTSU_TSF_R0_VAL_R 32
'
h0fffffff
`define
TXTSU_TSF_R0_VAL_F_OFFSET 28
`define
TXTSU_TSF_R0_VAL_F 32
'
hf0000000
`define
ADDR_TXTSU_TSF_R1 5
'
h14
`define
TXTSU_TSF_R1_PID_OFFSET 0
`define
TXTSU_TSF_R1_PID 32
'
h0000001f
`define
TXTSU_TSF_R1_FID_OFFSET 16
`define
TXTSU_TSF_R1_FID 32
'
hffff0000
`define
ADDR_TXTSU_TSF_R2 5
'
h18
`define
TXTSU_TSF_R2_INCORRECT_OFFSET 0
`define
TXTSU_TSF_R2_INCORRECT 32
'
h00000001
`define
ADDR_TXTSU_TSF_CSR 5
'
h1c
`define
TXTSU_TSF_CSR_FULL_OFFSET 16
`define
TXTSU_TSF_CSR_FULL 32
'
h00010000
`define
TXTSU_TSF_CSR_EMPTY_OFFSET 17
`define
TXTSU_TSF_CSR_EMPTY 32
'
h00020000
`define
TXTSU_TSF_CSR_USEDW_OFFSET 0
`define
TXTSU_TSF_CSR_USEDW 32
'
h000000ff
testbench/scb_top/main.sv
View file @
f0a792fa
...
...
@@ -3,6 +3,7 @@
`include
"tbi_utils.sv"
`include
"simdrv_wrsw_nic.svh"
`include
"simdrv_rtu.sv"
`include
"simdrv_txtsu.svh"
`include
"endpoint_regs.v"
`include
"endpoint_mdio.v"
`include
"if_wb_master.svh"
...
...
@@ -20,7 +21,7 @@ module main;
reg
clk_swc_mpm_core
=
0
;
reg
rst_n
=
0
;
parameter
g_num_ports
=
6
;
parameter
g_num_ports
=
18
;
// prameters to create some gaps between pks (not work really well)
parameter
g_enable_pck_gaps
=
0
;
//1=TRUE, 0=FALSE
...
...
@@ -53,7 +54,7 @@ module main;
// always #8ns clk_ref <= ~clk_ref;
initial
begin
repeat
(
3
)
@
(
posedge
clk_sys
)
;
repeat
(
100
)
@
(
posedge
clk_sys
)
;
rst_n
<=
1
;
end
/*
...
...
@@ -100,7 +101,7 @@ module main;
pkt
=
gen
.
gen
()
;
pkt
.
oob
=
TX_FID
;
$
display
(
"
Tx %d"
,
i
)
;
$
display
(
"
[port %d] tx %d"
,
srcPort
,
i
)
;
src
.
send
(
pkt
)
;
arr
[
i
]
=
pkt
;
...
...
@@ -160,6 +161,7 @@ module main;
port_t
ports
[$]
;
CSimDrv_NIC
nic
;
CRTUSimDriver
rtu
;
CSimDrv_TXTSU
txtsu
;
task
automatic
init_ports
(
ref
port_t
p
[$]
,
ref
CWishboneAccessor
wb
)
;
...
...
@@ -170,7 +172,7 @@ module main;
port_t
tmp
;
CSimDrv_WR_Endpoint
ep
;
ep
=
new
(
wb
,
'h30000
+
i
*
'h400
)
;
ep
.
init
()
;
ep
.
init
(
i
)
;
tmp
.
ep
=
ep
;
tmp
.
send
=
EthPacketSource
'
(
DUT
.
to_port
[
i
])
;
tmp
.
recv
=
EthPacketSink
'
(
DUT
.
from_port
[
i
])
;
...
...
@@ -185,7 +187,6 @@ module main;
nic
=
new
(
wb
,
'h20000
)
;
$
display
(
"NICInit"
)
;
nic
.
init
()
;
$
display
(
"Done"
)
;
...
...
@@ -199,7 +200,7 @@ module main;
endtask
// init_nic
initial
begin
uint64_t
msr
;
...
...
@@ -217,14 +218,21 @@ module main;
cpu_acc
.
set_mode
(
PIPELINED
)
;
cpu_acc
.
write
(
'h10304
,
(
1
<<
3
))
;
init_ports
(
ports
,
cpu_acc
)
;
$
display
(
"InitNIC"
)
;
init_nic
(
ports
,
cpu_acc
)
;
$
display
(
"InitTXTS"
)
;
txtsu
=
new
(
cpu_acc
,
'h51000
)
;
txtsu
.
init
()
;
$
display
(
"Initialization done"
)
;
rtu
=
new
;
rtu
.
set_bus
(
cpu_acc
,
'h60000
)
;
for
(
int
dd
=
0
;
dd
<
g_num_ports
;
dd
++
)
begin
...
...
@@ -232,8 +240,9 @@ module main;
end
rtu
.
add_static_rule
(
'
{
5
,
'h50
,
'hca
,
'hfe
,
'hba
,
'hbe
},
(
1
<<
2
))
;
rtu
.
add_static_rule
(
'
{
6
,
'h50
,
'hca
,
'hfe
,
'hba
,
'hbe
},
(
1
<<
1
))
;
rtu
.
add_static_rule
(
'
{
17
,
'h50
,
'hca
,
'hfe
,
'hba
,
'hbe
},
(
1
<<
17
))
;
rtu
.
add_static_rule
(
'
{
16
,
'h50
,
'hca
,
'hfe
,
'hba
,
'hbe
},
(
1
<<
16
))
;
// rtu.set_hash_poly();
def_vlan
.
port_mask
=
32'hffffffff
;
...
...
@@ -247,32 +256,39 @@ module main;
rtu
.
enable
()
;
////////////// sending packest on all the ports (16) according to the portUnderTest mask.///////
fork
//`ifdef none
begin
if
(
portUnderTest
[
6
])
begin
for
(
int
g
=
0
;
g
<
20
;
g
++
)
begin
$
display
(
"Try f_
6
:%d"
,
g
)
;
tx_test
(
seed
/* seed */
,
20
/* n_tries */
,
0
/* is_q */
,
0
/* unvid */
,
ports
[
6
]
.
send
/* src */
,
ports
[
1
]
.
recv
/* sink */
,
6
/* srcPort */
,
1
/* dstPort */
)
;
$
display
(
"Try f_
5
:%d"
,
g
)
;
tx_test
(
seed
/* seed */
,
20
0
/* n_tries */
,
0
/* is_q */
,
0
/* unvid */
,
ports
[
0
]
.
send
/* src */
,
ports
[
16
]
.
recv
/* sink */
,
0
/* srcPort */
,
16
/* dstPort */
)
;
end
end
end
// fork begin
`ifdef
none
//`endif // `ifdef none
// `ifdef none
begin
if
(
portUnderTest
[
5
])
begin
for
(
int
g
=
0
;
g
<
20
;
g
++
)
begin
$
display
(
"Try f_6:%d"
,
g
)
;
tx_test
(
seed
/* seed */
,
20
/* n_tries */
,
0
/* is_q */
,
0
/* unvid */
,
ports
[
5
]
.
send
/* src */
,
ports
[
2
]
.
recv
/* sink */
,
5
/* srcPort */
,
2
/* dstPort */
)
;
tx_test
(
seed
/* seed */
,
20
0
/* n_tries */
,
0
/* is_q */
,
0
/* unvid */
,
ports
[
1
]
.
send
/* src */
,
ports
[
17
]
.
recv
/* sink */
,
1
/* srcPort */
,
17
/* dstPort */
)
;
end
end
end
`endif
//
`endif
forever
begin
nic
.
update
(
DUT
.
U_Top
.
U_Wrapped_SCBCore
.
vic_irqs
[
0
])
;
@
(
posedge
clk_sys
)
;
end
forever
begin
txtsu
.
update
(
DUT
.
U_Top
.
U_Wrapped_SCBCore
.
vic_irqs
[
1
])
;
@
(
posedge
clk_sys
)
;
end
join_none
...
...
testbench/scb_top/scb_top_sim_svwrap.svh
View file @
f0a792fa
...
...
@@ -204,7 +204,7 @@ module scb_top_sim_svwrap
ep_acc
=
U_ep_wb
.
get_accessor
()
;
ep_drv
=
new
(
ep_acc
,
0
)
;
ep_drv
.
init
()
;
ep_drv
.
init
(
0
)
;
from_port
[
i
]
=
new
(
U_ep_snk
.
get_accessor
())
;
to_port
[
i
]
=
new
(
U_ep_src
.
get_accessor
())
;
...
...
testbench/scb_top/simdrv_wr_endpoint.svh
View file @
f0a792fa
...
...
@@ -39,8 +39,8 @@ class CSimDrv_WR_Endpoint;
`define
EP_QMODE_VLAN_DISABLED 3
task
init
()
;
m_acc
.
write
(
m_base
+
`ADDR_EP_ECR
,
`EP_ECR_TX_EN
|
`EP_ECR_RX_EN
)
;
task
init
(
int
port_id
)
;
m_acc
.
write
(
m_base
+
`ADDR_EP_ECR
,
`EP_ECR_TX_EN
|
`EP_ECR_RX_EN
|
(
port_id
<<
`EP_ECR_PORTID_OFFSET
))
;
m_acc
.
write
(
m_base
+
`ADDR_EP_RFCR
,
1518
<<
`EP_RFCR_MRU_OFFSET
)
;
m_acc
.
write
(
m_base
+
`ADDR_EP_VCR0
,
`EP_QMODE_VLAN_DISABLED
<<
`EP_VCR0_QMODE_OFFSET
)
;
m_acc
.
write
(
m_base
+
`ADDR_EP_TSCR
,
`EP_TSCR_EN_RXTS
|
`EP_TSCR_EN_TXTS
)
;
...
...
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