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White Rabbit Switch - Gateware
Commit 6c650238 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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[syn/top]: updated top levels/ISE projects for 8/18 port firmwares

parent 1b28e823
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syn/scb_15ports/test_scb.xise deleted 100644 → 0
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syn/scb_8ports/test_scb.xise
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top/scb_18ports/scb_top_synthesis.ucf
View file @ 6c650238
......@@ -278,6 +278,9 @@ NET "uart_sel_o" LOC="C12";
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
......@@ -1458,23 +1461,24 @@ TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/07/16
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
top/scb_18ports/scb_top_synthesis.vhd
View file @ 6c650238
......@@ -163,10 +163,14 @@ architecture Behavioral of scb_top_synthesis is
-- Clocks
-------------------------------------------------------------------------------
signal clk_sys_startup : std_logic;
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "0.5ns";
-----------------------------------------------------------------------------
-- Component declarations
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 6c650238
......@@ -255,6 +255,8 @@ NET "led_act_o[5]" LOC="AA25";
NET "led_act_o[6]" LOC="AB27";
NET "led_act_o[7]" LOC="AC27";
NET "clk_dmtd_divsel_o" LOC="AN15";
NET "uart_sel_o" LOC="C12";
NET "mbl_scl_b[0]" LOC="AF31";
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 6c650238
......@@ -99,6 +99,11 @@ entity scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
-- UART source selection (FPGA/DBGU)
uart_sel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
......@@ -249,6 +254,8 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
......@@ -490,7 +497,7 @@ begin
clk_gtx(1 downto 0) <= (others => clk_gtx16_19);
clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
--clk_gtx(11 downto 8) <= (others => clk_gtx8_11);
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
......@@ -572,6 +579,8 @@ begin
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
uart_sel_o => uart_sel_o,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
......
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