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White Rabbit Switch - Gateware
Commit cd61fa8a authored by José López Jiménez's avatar José López Jiménez
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Enable use of Main VCO power switch from GPIO controller

parent a4ce5847
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Showing with 18 additions and 14 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ cd61fa8a
......@@ -124,13 +124,16 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low jitter daughterboard AD9516
-- WRS Low jitter grandmaster AD9516
gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
-- Main Ref VCO power enable
p_3v3_vco_en_o : out std_logic;
-- Debug
......@@ -506,6 +509,7 @@ begin -- rtl
rst_n_o <= gpio_out(3);
gm_pll_reset_n_o <= gpio_out(4);
p_3v3_vco_en_o <= gpio_out(5);
-- gpio_in(5) <= ext_board_detected_i;
-- gpio_in(8 downto 6) <= ext_board_osc_freq_i;
......
top/bare_top/scb_top_bare.vhd
View file @ cd61fa8a
......@@ -156,7 +156,7 @@ entity scb_top_bare is
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
p_3v3_vco_en_o : out std_logic;
-- UART source selection (FPGA/DBGU)
uart_sel_o : out std_logic;
......@@ -580,6 +580,8 @@ begin
gm_pll_cs_n_o => gm_pll_cs_n_o,
gm_pll_sync_n_o => gm_pll_sync_n_o,
gm_pll_reset_n_o => gm_pll_reset_n_o,
p_3v3_vco_en_o => p_3v3_vco_en_o,
spll_dbg_o => spll_dbg_o);
......@@ -1156,7 +1158,6 @@ begin
clk_en_o <= '0';
clk_sel_o <= '0';
clk_dmtd_divsel_o <= '1'; -- choose 62.5 MHz DDMTD clock
clk_sys_o <= clk_sys;
-------------------------------------------------------------------------------
......
top/bare_top/wrsw_components_pkg.vhd
View file @ cd61fa8a
......@@ -200,7 +200,7 @@ package wrsw_components_pkg is
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
-- unused component? duplicate of the one in wrsw_top_pkg.vhd ?
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer);
......
top/bare_top/wrsw_top_pkg.vhd
View file @ cd61fa8a
......@@ -252,14 +252,13 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
-- ext_board_detected_i: in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
p_3v3_vco_en_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ cd61fa8a
......@@ -333,7 +333,7 @@ NET "mbl_sda_b[0]" LOC = AG32;
NET "mbl_scl_b[1]" LOC = AC25;
NET "mbl_sda_b[1]" LOC = AG31;
NET "clk_dmtd_divsel_o" LOC = AN15; # this signal actually enables power to the main VCO. 3v3_vco_en in schematics
NET "p_3v3_vco_en_o" LOC = AN15;
NET "mb_fan1_pwm_o" LOC = C12; # fan box pwm
NET "mb_fan2_pwm_o" LOC = D12; # fan power supply
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ cd61fa8a
......@@ -158,7 +158,7 @@ entity scb_top_synthesis is
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
p_3v3_vco_en_o : out std_logic;
-- UART source selection (FPGA/DBGU)
-- uart_sel_o : out std_logic;
......@@ -374,7 +374,7 @@ architecture Behavioral of scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
p_3v3_vco_en_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
......@@ -829,7 +829,7 @@ begin
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
-- uart_sel_o => uart_sel_o,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
p_3v3_vco_en_o => p_3v3_vco_en_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
......
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