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White Rabbit Switch - Gateware
Commit a4ce5847 authored by José López Jiménez's avatar José López Jiménez
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Added capabilities for another DAC in SoftPLL and its associated regs

parent b86f3d0f
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Showing with 9 additions and 3 deletions
wr-cores @ 3add48fc
Subproject commit 2ee4e55bb7658f349be95970016f5774d04af042
Subproject commit 3add48fcf066192d90888fb915134f1bd3a311c2
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ a4ce5847
......@@ -169,6 +169,8 @@ architecture rtl of wrsw_rt_subsystem is
dac_out_data_o : out std_logic_vector(15 downto 0);
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
dac_ho_data_o : out std_logic_vector(15 downto 0);
dac_ho_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
......@@ -261,6 +263,8 @@ architecture rtl of wrsw_rt_subsystem is
signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_out_load, dac_dmtd_load : std_logic;
signal dac_ho_data : std_logic_vector(15 downto 0);
signal dac_ho_load : std_logic;
signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic;
......@@ -376,6 +380,8 @@ begin -- rtl
dac_out_data_o => dac_out_data,
dac_out_sel_o => open,
dac_out_load_o => dac_out_load,
dac_ho_data_o => dac_ho_data,
dac_ho_load_o => dac_ho_load,
out_enable_i => "0",
out_locked_o => open,
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
......@@ -531,9 +537,9 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
value_i => dac_out_data,
value_i => dac_ho_data,
cs_sel_i => "1",
load_i => dac_out_load,
load_i => dac_ho_load,
sclk_divsel_i => "010",
dac_cs_n_o(0) => ho_dac_sync_n_o,
dac_sclk_o => ho_dac_sclk_o,
......
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