wrsw_rt_subsystem: use 62.5 MHz DDMTD clock

c8977c3f · Tomasz Wlostowski · f719aca3 · c8977c3f
Commit c8977c3f authored Jul 24, 2012 by Tomasz Wlostowski
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wrsw_rt_subsystem.vhd modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd +1 -1

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--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -282,7 +282,7 @@ begin  -- rtl
      g_num_outputs          => 1,
      g_reverse_dmtds        => true,
      g_with_ext_clock_input => true,
-      g_divide_input_by_2    => true,
+      g_divide_input_by_2    => false,
      g_with_period_detector => false,
      g_with_undersampling   => false,
      g_with_debug_fifo      => true,