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White Rabbit Switch - Gateware
Commit f719aca3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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[syn/top]/scb_18ports: working 18-ports FW (DDMTD local clock still to-be-fixed)

parent 77e46e44
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syn/scb_18ports/test_scb.xise
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top/scb_18ports/scb_top_synthesis.ucf
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top/scb_18ports/scb_top_synthesis.vhd
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......@@ -100,6 +100,12 @@ entity scb_top_synthesis is
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
-- UART source selection (FPGA/DBGU)
uart_sel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
---------------------------------------------------------------------------
......@@ -243,6 +249,8 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
......@@ -565,6 +573,8 @@ begin
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
uart_sel_o => uart_sel_o,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
......
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