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White Rabbit Switch - Gateware
Commit afec48f3 authored by Konstantinos Blantos's avatar Konstantinos Blantos
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Update .gitlab-ci.yml

parent 378f2311
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.gitlab-ci.yml
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......@@ -58,26 +58,26 @@ job_scb_top_8p_sim:
# - syn/scb_8ports/*.par
# - syn/scb_8ports/*.twr
job_scb_top_18p_syn:
stage: syn
tags:
- xilinx_ISE_14.7
script:
- /entrypoint.sh
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
- cat synthesis_descriptor.vhd
- cd ../../syn/scb_18ports
- hdlmake makefile
- make
artifacts:
name: SCB_TOP_8P_CI_$CI_JOB_ID
paths:
- syn/scb_18ports/*.syr
- syn/scb_18ports/*.mrp
- syn/scb_18ports/*.bit
- syn/scb_18ports/*.bin
- syn/scb_18ports/*.par
- syn/scb_18ports/*.twr
#job_scb_top_18p_syn:
# stage: syn
# tags:
# - xilinx_ISE_14.7
# script:
# - /entrypoint.sh
# - source ~/setup_ise147.sh
# - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cat synthesis_descriptor.vhd
# - cd ../../syn/scb_18ports
# - hdlmake makefile
# - make
# artifacts:
# name: SCB_TOP_8P_CI_$CI_JOB_ID
# paths:
# - syn/scb_18ports/*.syr
# - syn/scb_18ports/*.mrp
# - syn/scb_18ports/*.bit
# - syn/scb_18ports/*.bin
# - syn/scb_18ports/*.par
# - syn/scb_18ports/*.twr
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