BD + project TCL for AFCZ

9c4063bd · Tomasz Wlostowski · bfefdf29 · 9c4063bd · 9c4063bd · bfefdf29
Commit 9c4063bd authored Oct 31, 2023 by Tomasz Wlostowski
12 changed files
--- a/syn/zynq_us/scb_8ports/afcz_scb_8ports/bd.tcl
+++ b/syn/zynq_us/scb_8ports/afcz_scb_8ports/bd.tcl
@@ -1743,5 +1743,3 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_
 create_root_design ""


-common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
-
--- a/syn/afcz_scb_8ports/project.tcl
+++ b/syn/afcz_scb_8ports/project.tcl
--- a/syn/zynq_us/scb_8ports/afcz_scb_8ports/project.tcl
+++ b/syn/zynq_us/scb_8ports/afcz_scb_8ports/project.tcl
--- a/top/afcz_wrs_8p/Manifest.py
+++ b/top/afcz_wrs_8p/Manifest.py
+files = [ "afcz_wrs_8p_top.vhd", "pins.xdc", "timing.xdc" ];
+
+modules = { "local" : [ "../..", "../bare_top" ] };
--- a/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
+++ b/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
--- a/top/zynq_us/scb_8ports/bd.tcl
+++ b/top/zynq_us/scb_8ports/bd.tcl
--- a/top/zynq_us/scb_8ports/pins.xdc
+++ b/top/zynq_us/scb_8ports/pins.xdc
--- a/top/zynq_us/scb_8ports/project.tcl
+++ b/top/zynq_us/scb_8ports/project.tcl
--- a/top/afcz_wrs_8p/timing.xdc
+++ b/top/afcz_wrs_8p/timing.xdc
+
+
+
+#
+
+
+
+
+
+
+
+create_clock -period 8.000 -name mgtclk1_224_p_i -waveform {0.000 4.000} [get_ports mgtclk1_224_p_i]
+create_clock -period 50.000 -name clk_20m_vcxo1_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo1_i]
+set_false_path -from [get_clocks I] -to [get_clocks {from_phys[0][tx_out_clk]}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_1}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_2}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_3}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_4}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_5}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_6}]
+set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_7}]
+create_clock -period 16.000 -name clk_rx0 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[0].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx1 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[1].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx2 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[2].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx3 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[3].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx4 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[4].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx5 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[5].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx6 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[6].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_clock -period 16.000 -name clk_rx7 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[7].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
+create_generated_clock -name clk_dmtd_62_5 -source [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKIN1] -master_clock clk_20m_vcxo1_i [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKOUT0]
+
+
+
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-02-21
-- Last update: 2020-08-18
+-- Last update: 2023-10-31
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -778,8 +778,8 @@ begin

          phy_rst_o          => phys_o(i).rst,
          phy_loopen_o       => phys_o(i).loopen,
-          phy_lpc_stat_i     => phys_i(i).lpc_stat,
-          phy_lpc_ctrl_o     => phys_o(i).lpc_ctrl,
+--          phy_lpc_stat_i     => phys_i(i).lpc_stat,
+--          phy_lpc_ctrl_o     => phys_o(i).lpc_ctrl,
          phy_rdy_i          => phys_i(i).rdy,
          phy_ref_clk_i      => phys_i(i).ref_clk,
          phy_tx_data_o      => ep_dbg_data_array(i), -- phys_o(i).tx_data, --

--- a/top/zynq_us/scb_8ports/Manifest.py
+++ b/top/zynq_us/scb_8ports/Manifest.py
-files = [ "afcz_wrs_8p_top.vhd" ];
-
-modules = { "local" : [ "../../../", "../../bare_top",
-"../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4"
-  ] };
--- a/top/zynq_us/scb_8ports/timing.xdc
+++ b/top/zynq_us/scb_8ports/timing.xdc