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White Rabbit Switch - Gateware
Commit 9c4063bd authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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BD + project TCL for AFCZ

parent bfefdf29
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Showing with 580 additions and 5670 deletions
syn/zynq_us/scb_8ports/afcz_scb_8ports/bd.tcl → syn/afcz_scb_8ports/bd.tcl
View file @ 9c4063bd
......@@ -1743,5 +1743,3 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_
create_root_design ""
common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
syn/afcz_scb_8ports/project.tcl 0 → 100644
View file @ 9c4063bd
#*****************************************************************************************
# Vivado (TM) v2018.2 (64-bit)
#
# project.tcl: Tcl script for re-creating project 'afcz_scb_8ports'
#
# Generated by Vivado on Thu Sep 28 14:08:29 CEST 2023
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (project.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "/home/twl/wr-repos/wr-switch-hdl/syn/zynq_us/scb_8ports/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd"
# "/home/twl/wr-repos/wr-switch-hdl/syn/zynq_us/scb_8ports/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/hdl/top_wrapper.v"
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/utils.vh"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/dpram.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/dpram_bbs.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_1ht.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_bin.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/lvt_reg.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_lvt.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_reg.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mrram.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mrram_swt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/PCK_CRC16_D16.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_shared_types_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrsw_top_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/axi/axi4_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwinfo_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tru/tru_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tru/wrsw_tru_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/synthesis_descriptor.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrs_sdb_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/scb_top_bare.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/gen10_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/gen10_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/gw_ver_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/irq_ram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_private_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_read_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/mpm/mpm_write_path.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/pack_unpack_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/port_cntr.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/pstats_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_crc_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_crc.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_fast_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_lookup_engine.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_match.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_port_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_swcore_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_alloc_resource_manager.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_ll_read_data_validation.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_multiport_linked_list.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_ob_prio_queue.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_output_queue_scheduler.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_output_traffic_shaper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_pg_free_module.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_input.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_pck_transfer_output.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_prio_encoder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/wdog_wbgen2_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/wdog_wishbone_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/wrsw_pstats.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_core.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_input_block.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/xswc_output_block_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/xwrsw_hwiu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_pstats/xwrsw_pstats.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/xwrsw_rtu_new.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_watchdog/xwrsw_watchdog.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_gthe4.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_bit_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_sync.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/bare_top/wrsw_components_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_reset.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/matrix_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_delay_line.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_comparator.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_top.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_rx_buffer_bypass.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/example/gtwizard_ultrascale_2_example_wrapper.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_reset.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gc_reset_synchronizer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_flow_control.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rmon_counters.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/xwrsw_rtu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_components_pkg.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/wrsw_rtu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_rtu/rtu_port.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/Switched-Multiported-RAM/mpram_xor.v"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_rr_arbiter.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_swcore/swc_core.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/modules/wrsw_hwiu/wrsw_hwiu.vhd"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/timing.xdc"
# "/home/twl/wr-repos/wr-switch-hdl/top/zynq_us/scb_8ports/pins.xdc"
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "afcz_scb_8ports"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "project.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu7ev-ffvf1517-2-e
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/ies" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/modelsim" -objects $obj
set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/questa" -objects $obj
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/riviera" -objects $obj
set_property -name "compxlib.timesim" -value "1" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/vcs" -objects $obj
set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
set_property -name "dsa.flash_size" -value "1024" -objects $obj
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
set_property -name "dsa.rom.debug_type" -value "0" -objects $obj
set_property -name "dsa.rom.prom_type" -value "0" -objects $obj
set_property -name "dsa.uses_pr" -value "1" -objects $obj
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
set_property -name "dsa.version" -value "0.0" -objects $obj
set_property -name "enable_core_container" -value "1" -objects $obj
set_property -name "enable_optional_runs_sta" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_interface_inference_priority" -value "" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xczu7ev-ffvf1517-2-e" -objects $obj
set_property -name "project_type" -value "Default" -objects $obj
set_property -name "pr_flow" -value "0" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "source_mgmt_mode" -value "All" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
set_property -name "target_simulator" -value "XSim" -objects $obj
set_property -name "tool_flow" -value "Vivado" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
set_property -name "xsim.array_display_limit" -value "1024" -objects $obj
set_property -name "xsim.radix" -value "hex" -objects $obj
set_property -name "xsim.time_unit" -value "ns" -objects $obj
set_property -name "xsim.trace_limit" -value "65536" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
source files.tcl
source bd.tcl
update_compile_order -fileset sources_1
make_wrapper -files [get_files ${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd] -top
# Add local files from the original project (-no_copy_sources specified)
set files [list \
[file normalize "${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/top.bd" ]\
[file normalize "${origin_dir}/afcz_scb_8ports/afcz_scb_8ports.srcs/sources_1/bd/top/hdl/top_wrapper.v" ]\
]
add_files -fileset sources_1 $files
set obj [get_filesets sources_1]
set_property -name "design_mode" -value "RTL" -objects $obj
set_property -name "edif_extra_search_paths" -value "" -objects $obj
set_property -name "elab_link_dcps" -value "1" -objects $obj
set_property -name "elab_load_timing_constraints" -value "1" -objects $obj
set_property -name "generic" -value "" -objects $obj
set_property -name "include_dirs" -value "" -objects $obj
set_property -name "lib_map_file" -value "" -objects $obj
set_property -name "loop_count" -value "1000" -objects $obj
set_property -name "name" -value "sources_1" -objects $obj
set_property -name "top" -value "top_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "verilog_define" -value "" -objects $obj
set_property -name "verilog_uppercase" -value "0" -objects $obj
set_property -name "verilog_version" -value "verilog_2001" -objects $obj
set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj
syn/zynq_us/scb_8ports/afcz_scb_8ports/project.tcl deleted 100644 → 0
View file @ bfefdf29
This source diff could not be displayed because it is too large. You can view the blob instead.
top/afcz_wrs_8p/Manifest.py 0 → 100644
View file @ 9c4063bd
files = [ "afcz_wrs_8p_top.vhd", "pins.xdc", "timing.xdc" ];
modules = { "local" : [ "../..", "../bare_top" ] };
top/afcz_wrs_8p/timing.xdc 0 → 100644
View file @ 9c4063bd
#
create_clock -period 8.000 -name mgtclk1_224_p_i -waveform {0.000 4.000} [get_ports mgtclk1_224_p_i]
create_clock -period 50.000 -name clk_20m_vcxo1_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo1_i]
set_false_path -from [get_clocks I] -to [get_clocks {from_phys[0][tx_out_clk]}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_1}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_2}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_3}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_4}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_5}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_6}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_7}]
create_clock -period 16.000 -name clk_rx0 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[0].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx1 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[1].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx2 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[2].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx3 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[3].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx4 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[4].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx5 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[5].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx6 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[6].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx7 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[7].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_generated_clock -name clk_dmtd_62_5 -source [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKIN1] -master_clock clk_20m_vcxo1_i [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKOUT0]
top/bare_top/scb_top_bare.vhd
View file @ 9c4063bd
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2020-08-18
-- Last update: 2023-10-31
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -778,8 +778,8 @@ begin
phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen,
phy_lpc_stat_i => phys_i(i).lpc_stat,
phy_lpc_ctrl_o => phys_o(i).lpc_ctrl,
-- phy_lpc_stat_i => phys_i(i).lpc_stat,
-- phy_lpc_ctrl_o => phys_o(i).lpc_ctrl,
phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
......
top/zynq_us/scb_8ports/Manifest.py deleted 100644 → 0
View file @ bfefdf29
files = [ "afcz_wrs_8p_top.vhd" ];
modules = { "local" : [ "../../../", "../../bare_top",
"../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4"
] };
top/zynq_us/scb_8ports/timing.xdc deleted 100644 → 0
View file @ bfefdf29
#
create_clock -period 8.000 -name mgtclk1_224_p_i -waveform {0.000 4.000} [get_ports mgtclk1_224_p_i]
create_clock -period 50.000 -name clk_20m_vcxo1_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo1_i]
set_false_path -from [get_clocks I] -to [get_clocks {from_phys[0][tx_out_clk]}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_1}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_2}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_3}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_4}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_5}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_6}]
set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_7}]
create_clock -period 16.000 -name clk_rx0 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[0].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx1 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[1].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx2 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[2].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx3 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[3].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx4 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[4].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx5 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[5].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx6 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[6].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_clock -period 16.000 -name clk_rx7 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[7].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_generated_clock -name clk_dmtd_62_5 -source [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKIN1] -master_clock clk_20m_vcxo1_i [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKOUT0]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list top_i/cmp_zynq/inst/pl_clk0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[2]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[3]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[4]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[5]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[6]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[2]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[3]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[4]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[5]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[6]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 32 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[sel][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[ack]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[err]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[stall]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[cyc]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[stb]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[we]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_ack_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_cyc_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_rst_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_stb_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_we_i]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
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