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White Rabbit Switch - Gateware
Commit 7ff88d15 authored by Maciej Lipinski's avatar Maciej Lipinski
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working check of link-down at different moments of frame rx

parent 39cccfb9
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testbench/scb_top/main.sv
View file @ 7ff88d15
......@@ -2832,28 +2832,64 @@ module main;
* - enable FastForward for broadcast
* -
**/
///*
// initial begin
// portUnderTest = 18'b000000000000000011;
// // tx ,rx ,opt
// trans_paths[0] = '{0 ,1 , 1 };
// trans_paths[1] = '{1 ,0 , 1 };
// repeat_number = 10000;
// tries_number = 1;
// g_enable_pck_gaps = 0;
// g_force_payload_size = 249-18; // header = 14 bytes | CRC = 4 bytes
//
//
// sim_vlan_tab[ 0] = '{'{32'hFFFFFFFF, 8'h0 , 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
// sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
// g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
//
// rx_forward_on_fmatch_full = 1;
// mac_br = 1;
// mac_single = 1;
// g_is_qvlan = 0;
// g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
// g_set_untagging = 2; // untagging
/** *************************** test scenario 82 ************************************* **/
/* BTrain problem
* send frames from port 0 to 1:
* - vlan on ports 0 & 1
* - tag/untagg
* - send broadcast
* - enable FastForward for broadcast
* -
**/
///*
initial begin
portUnderTest = 18'b000000000000000011;
portUnderTest = 18'b000000000000000001;
// tx ,rx ,opt
trans_paths[0] = '{0 ,1 , 1 };
trans_paths[1] = '{1 ,0 , 1 };
repeat_number = 10000;
tries_number = 1;
g_enable_pck_gaps = 0;
g_force_payload_size = 249-18; // header = 14 bytes | CRC = 4 bytes
g_enable_pck_gaps = 1;
g_min_pck_gap = 214;
g_max_pck_gap = 214; // to make it 250kHz
g_force_payload_size = 64-18; // header = 14 bytes | CRC = 4 bytes
sim_vlan_tab[ 0] = '{'{32'hFFFFFFFF, 8'h0 , 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
// sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
rx_forward_on_fmatch_full = 1;
mac_br = 1;
mac_single = 1;
g_is_qvlan = 0;
g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
g_do_vlan_config = 0; // snake EP configuration (tagging proper VLANs on ports
g_set_untagging = 2; // untagging
g_failure_scenario = 14;
g_ignore_rx_test_check = 1;
end
//*/
......@@ -2885,7 +2921,7 @@ module main;
end
endtask // wait_cycles
task automatic tx_test(ref int seed, input int n_tries, input int is_q,input int unvid, ref EthPacketSource src, ref EthPacketSink sink, input int srcPort, input int dstPort, input int opt=0);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl, pkt2;
......@@ -4088,7 +4124,71 @@ module main;
hwdu.dump_mpm_page_utilization(1);
wait_cycles(1000);
hwdu.dump_mpm_page_utilization(1);
end
if(g_failure_scenario == 12) // btrain problem
begin
wait_cycles(1998);
ep_ctrl[0] = 'b0;
$display("");
$display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
$display("");
end
if(g_failure_scenario == 13) // btrain problem - break link with respect to INPUT BLOCK state machine
begin
automatic int cnt_ld =0;
automatic int timeout = 2000;
automatic integer i;
for(cnt_ld=100;cnt_ld>0;cnt_ld--)
begin
$display("test with delay %d cycles\n", cnt_ld );
for(i=0;i<timeout;i=i+1)
begin
if (DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rcv_p_FSM == 3) break;
@(posedge clk_sys);
end
wait_cycles(cnt_ld);
ep_ctrl[0] = 'b0;
$display("");
$display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
$display("");
wait_cycles(100);
ep_ctrl[0] = 'b1;
$display("");
$display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 up <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
$display("");
wait_cycles(10);
end
end
if(g_failure_scenario == 14) // btrain problem - break link with respect to rx frame
begin
automatic int cnt_ld =0;
automatic int timeout = 2000;
automatic integer i;
for(cnt_ld=1;cnt_ld<100;cnt_ld++)
begin
wait_cycles(300);
$display("test with delay %d cycles\n", cnt_ld );
for(i=0;i<timeout;i=i+1)
begin
if (DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X.phy_rx_data_i == 16'hFFFF) break;
@(posedge clk_sys);
end
wait_cycles(cnt_ld);
ep_ctrl[0] = 'b0;
$display("");
$display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
$display("");
wait_cycles(100);
ep_ctrl[0] = 'b1;
$display("");
$display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 up <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
$display("");
wait_cycles(200);
end
end
end
join_none; //
......
testbench/scb_top/run.do
View file @ 7ff88d15
# make -f Makefile
#make -f Makefile
vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
set StdArithNoWarnings 1
......
testbench/scb_top/scb_top_sim_svwrap.svh
View file @ 7ff88d15
......@@ -306,7 +306,7 @@ module scb_top_sim_svwrap
tx_k_invalid[j] = 2'b01 ;
end
else begin //including 0
$display("Link failure type: 0 [simply off the link: data='h00BC, k = 'b01]");
// $display("Link failure type: 0 [simply off the link: data='h00BC, k = 'b01]");
tx_data_invalid[j] = 'h00BC;
tx_k_invalid[j] = 2'b01 ;
end
......
testbench/scb_top/wave.do
View file @ 7ff88d15
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