[SIM] make the top simulation work again

39cccfb9 · Maciej Lipinski · d315bf7b · 39cccfb9 · 39cccfb9 · 39cccfb9
Commit 39cccfb9 authored Jan 08, 2021 by Maciej Lipinski
4 changed files
--- a/modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd
@@ -60,7 +60,7 @@ end wrsw_ljd_detect;

 architecture Behavioral of wrsw_ljd_detect is

-  signal clk_divider    : integer range 0 to g_clk_divider-1;
+  signal clk_divider    : integer range 0 to g_clk_divider;---1;
  signal clk_en         : std_logic;
  signal bit_position   : integer range 0 to g_pattern'length-1;
  signal error_detected : std_logic;

--- a/testbench/scb_top/run.do
+++ b/testbench/scb_top/run.do
-make -f Makefile
-#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
+# make -f Makefile
+vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
 vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1

--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
@@ -189,7 +189,7 @@ begin  -- rtl
      clk_dmtd_i          => clk_dmtd_i,
 --      clk_sys_i           => clk_sys_i,
      clk_aux_i           => clk_aux_i,
-      clk_ext_mul_i       => '0',
+      clk_ext_mul_i       => "00",
      clk_ext_mul_locked_i=> '1',
      cpu_wb_i            => cpu_wb_in,
      cpu_wb_o            => cpu_wb_out,
@@ -224,7 +224,12 @@ begin  -- rtl
      i2c_scl_i       => i2c_scl_in,
      i2c_sda_oen_o   => i2c_sda_oen,
      i2c_sda_o       => i2c_sda_out,
-      i2c_sda_i       => i2c_sda_in
+      i2c_sda_i       => i2c_sda_in,
+
+      ljd_loopback_i  => '0',
+      ljd_osc_freq_i  => "000",
+      ljd_pll_miso_i  => '0',
+      ljd_pll_locked_i=> '0'
      );

  gen_phys : for i in 0 to g_num_ports-1 generate

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -348,8 +348,8 @@ package wrsw_top_pkg is
      clk_ref_i           : in  std_logic;
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
-      clk_ext_mul_i       : in  std_logic := '0';
-      clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
+      clk_ext_mul_i       : in std_logic_vector(1 downto 0) := (others=>'0');
+      clk_ext_mul_locked_i : in  std_logic := '0';
      clk_sys_o           : out std_logic;
      cpu_wb_i            : in  t_wishbone_slave_in;
      cpu_wb_o            : out t_wishbone_slave_out;