Skip to content

W
White Rabbit Switch - Gateware
Commit 5c2f1c1f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

ported to wrpcv5 RT subsystem (RISC-V)

parent ee6d6782
Hide whitespace changes
Inline Side-by-side
Showing with 75 additions and 31 deletions
.gitmodules
View file @ 5c2f1c1f
......@@ -4,3 +4,6 @@
[submodule "ip_cores/wr-cores"]
path = ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "ip_cores/urv-core"]
path = ip_cores/urv-core
url = https://ohwr.org/project/urv-core.git
Manifest.py
View file @ 5c2f1c1f
......@@ -10,5 +10,6 @@ modules = { "local" : [
"platform/virtex6/chipscope",
"platform/xilinx",
"ip_cores/wr-cores",
"ip_cores/general-cores"],
"ip_cores/general-cores",
"ip_cores/urv-core"],
};
urv-core @ 802c1532
Subproject commit 802c1532a077b801b111f7d45be5c86e6792e023
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 5c2f1c1f
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2020-08-18
-- Last update: 2023-11-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -187,22 +187,22 @@ architecture rtl of wrsw_rt_subsystem is
slave_o : out t_wishbone_slave_out);
end component;
-- interconnect layout:
-- 0x00000 - 0x10000: RAM
-- 0x10000 - 0x01000: mailbox
-- 0x10000 - 0x10100: UART
-- 0x10100 - 0x10200: SoftPLL
-- 0x10200 - 0x10300: SPI master (to PLL)
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
-- 0x10500 - 0x10600: uRV loader regs
constant c_NUM_GPIO_PINS : integer := 32;
constant c_NUM_WB_SLAVES : integer := 10;
constant c_NUM_WB_SLAVES : integer := 11;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
constant c_MASTER_URV : integer := 1;
constant c_SLAVE_DPRAM : integer := 0;
constant c_SLAVE_MAILBOX_DPRAM : integer := 0;
constant c_SLAVE_UART : integer := 1;
constant c_SLAVE_SOFTPLL : integer := 2;
constant c_SLAVE_SPI : integer := 3;
......@@ -211,7 +211,8 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
constant c_SLAVE_SI57X : integer := 9;
constant c_SLAVE_SI57X : integer := 9;
constant c_SLAVE_URV_BOOT_REGS : integer := 10;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -275,21 +276,23 @@ begin -- rtl
master_i => cnx_master_in,
master_o => cnx_master_out);
U_CPU : xwb_lm32
U_CPU : entity work.wrc_urv_wrapper
generic map (
g_profile => "medium_icache_debug")
g_IRAM_SIZE => 16384,
g_IRAM_INIT => "",
g_CPU_ID => 0)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => cpu_reset_n,
irq_i => cpu_irq_vec,
dwb_o => cnx_slave_in(c_MASTER_LM32),
dwb_i => cnx_slave_out(c_MASTER_LM32),
iwb_o => cpu_iwb_out,
iwb_i => cpu_iwb_in);
U_DPRAM : xwb_dpram
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
irq_i => cpu_irq_vec(0),
dwb_o => cnx_slave_in(c_MASTER_URV),
dwb_i => cnx_slave_out(c_MASTER_URV),
host_slave_i => cnx_master_out(c_SLAVE_URV_BOOT_REGS),
host_slave_o => cnx_master_in(c_SLAVE_URV_BOOT_REGS));
U_Mailbox_DPRAM : xwb_dpram
generic map (
g_size => 16384,
g_size => 1024,
g_init_file => "",
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
......@@ -298,10 +301,10 @@ begin -- rtl
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave1_i => cnx_master_out(c_SLAVE_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_DPRAM),
slave2_i => cpu_iwb_out,
slave2_o => cpu_iwb_in);
slave1_i => cnx_master_out(c_SLAVE_MAILBOX_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_MAILBOX_DPRAM),
slave2_i => cc_dummy_slave_in
);
U_UART : xwb_simple_uart
generic map (
......
syn/afcz_scb_8ports/files.tcl
View file @ 5c2f1c1f
......@@ -201,6 +201,24 @@ add_files -norecurse {
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
../../ip_cores/urv-core/rtl/urv_cpu.v
../../ip_cores/urv-core/rtl/urv_csr.v
../../ip_cores/urv-core/rtl/urv_decode.v
../../ip_cores/urv-core/rtl/urv_divide.v
../../ip_cores/urv-core/rtl/urv_ecc.v
../../ip_cores/urv-core/rtl/urv_exceptions.v
../../ip_cores/urv-core/rtl/urv_exec.v
../../ip_cores/urv-core/rtl/urv_fetch.v
../../ip_cores/urv-core/rtl/urv_iram.v
../../ip_cores/urv-core/rtl/urv_multiply.v
../../ip_cores/urv-core/rtl/urv_pkg.vhd
../../ip_cores/urv-core/rtl/urv_regfile.v
../../ip_cores/urv-core/rtl/urv_shifter.v
../../ip_cores/urv-core/rtl/urv_timer.v
../../ip_cores/urv-core/rtl/urv_writeback.v
../../ip_cores/urv-core/rtl/urv_defs.v
../../ip_cores/urv-core/rtl/urv_config.v
../../ip_cores/urv-core/rtl/xurv_core.vhd
../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd
......
testbench/wrsw_rt_subsystem/Manifest.py
View file @ 5c2f1c1f
......@@ -2,13 +2,15 @@ target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
syn_device = "xczu9"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl", "../../ip_cores/general-cores/modules/wishbone/wb_spi/", "../../modules/wrsw_swcore/Switched-Multiported-RAM/", "../../ip_cores/urv-core/rtl/",
"../../ip_cores/general-cores/sim/" ]
modules = { "local" : ["../../top/bare_top",
"../../ip_cores/general-cores",
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ 5c2f1c1f
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2014-09-16
-- Last update: 2020-07-28
-- Last update: 2023-11-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -252,11 +252,27 @@ package wrs_sdb_pkg is
date => x"20160810",
name => "WR-si57x-interface ")));
constant c_xwr_urv_boot_regs_sdb: t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7",
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"1234dead", -- echo -n "xswc_core" | md5sum - | cut -c1-8
version => x"00000001",
date => x"20160810",
name => "WR-urv-boot-regs ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(9 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
constant c_rtbar_layout : t_sdb_record_array(10 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(1024), x"00000000"), -- mailbox
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
3 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010200"), --SPI
......@@ -265,8 +281,8 @@ package wrs_sdb_pkg is
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700"), --SPI ext
9 => f_sdb_embed_device(c_xwr_si57x_interface_sdb, x"00010800") -- si57x
9 => f_sdb_embed_device(c_xwr_si57x_interface_sdb, x"00010800"), -- si57x
10 => f_sdb_embed_device(c_xwr_urv_boot_regs_sdb, x"00010900") -- urvboot
);
constant c_rtbar_sdb_address : t_wishbone_address := x"00011000";
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment